Home
last modified time | relevance | path

Searched refs:DDRC_TIMING (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dsdram.c236 writel(ddr_config->timing[i], ddr_ctl_regs + DDRC_TIMING(i)); in sdram_init()
/openbmc/u-boot/arch/mips/mach-jz47xx/include/mach/
H A Djz4780_dram.h31 #define DDRC_TIMING(n) (0x60 + 4 * (n)) macro