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Searched refs:DDRC_SWCTL (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A Dlpddr4_init.c93 reg32_write(DDRC_SWCTL(0), 0x00000000); in ddr_init()
105 reg32_write(DDRC_SWCTL(0), 0x00000001); in ddr_init()
123 reg32_write(DDRC_SWCTL(0), 0x00000000); in ddr_init()
135 reg32_write(DDRC_SWCTL(0), 0x00000001); in ddr_init()
142 reg32_write(DDRC_SWCTL(0), 0x00000000); in ddr_init()
164 reg32_write(DDRC_SWCTL(0), 0x00000001); in ddr_init()
H A Dddr4_init.c69 reg32_write(DDRC_SWCTL(0), 0x00000000); in ddr_init()
97 reg32_write(DDRC_SWCTL(0), 0x00000001); in ddr_init()
/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c117 { DDRC_SWCTL(0), 0x00000001 },
H A Dlpddr4_timing.c80 { DDRC_SWCTL(0), 0x00000001 },
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h484 #define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320) macro