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Searched refs:DDRC_STAT (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A Dddr4_init.c55 while (0 != (0x7 & reg32_read(DDRC_STAT(0)))) in ddr_init()
103 while (0x1 != (0x7 & reg32_read(DDRC_STAT(0)))) in ddr_init()
H A Dlpddr4_init.c87 tmp = reg32_read(DDRC_STAT(0)); in ddr_init()
176 tmp = reg32_read(DDRC_STAT(0)); in ddr_init()
/openbmc/u-boot/arch/arm/mach-imx/mx7/
H A Dpsci-mx7.c76 #define DDRC_STAT 0x4 macro
532 while ((readl(DDRC_IPS_BASE_ADDR + DDRC_STAT) & 0x23) != 0x23) in imx_ddrc_enter_self_refresh()
541 while ((readl(DDRC_IPS_BASE_ADDR + DDRC_STAT) & 0x3) == 0x3) in imx_ddrc_exit_self_refresh()
/openbmc/u-boot/board/toradex/colibri_imx7/
H A Dimximage.cfg148 /* DDRC_STAT */
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h360 #define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04) macro