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Searched refs:DDRC_SCHED1 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c108 { DDRC_SCHED1(0), 0x0000002c },
H A Dlpddr4_timing.c73 { DDRC_SCHED1(0), 0x0000002c },
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h467 #define DDRC_SCHED1(X) (DDRC_IPS_BASE_ADDR(X) + 0x254) macro