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Searched refs:DDRC_RFSHCTL3 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A Dddr4_init.c61 reg32_write(DDRC_RFSHCTL3(0), 0x00000001); in ddr_init()
109 reg32_write(DDRC_RFSHCTL3(0), 0x00000000); in ddr_init()
H A Dlpddr4_init.c81 reg32_write(DDRC_RFSHCTL3(0), 0x00000011); in ddr_init()
180 reg32_write(DDRC_RFSHCTL3(0), 0x00000010); in ddr_init()
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h377 #define DDRC_RFSHCTL3(X) (DDRC_IPS_BASE_ADDR(X) + 0x60) macro