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Searched refs:DDRC_PWRCTL (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A Dddr4_init.c53 reg32_write(DDRC_PWRCTL(0), 0x00000001); in ddr_init()
68 reg32_write(DDRC_PWRCTL(0), 0x00000aa); in ddr_init()
91 reg32_write(DDRC_PWRCTL(0), 0x0000088); in ddr_init()
106 reg32_write(DDRC_PWRCTL(0), 0x0000088); in ddr_init()
H A Dlpddr4_init.c84 reg32_write(DDRC_PWRCTL(0), 0x000000a8); in ddr_init()
162 reg32_write(DDRC_PWRCTL(0), 0x00000008); in ddr_init()
/openbmc/u-boot/arch/arm/mach-imx/mx7/
H A Dpsci-mx7.c77 #define DDRC_PWRCTL 0x30 macro
527 writel(0, DDRC_IPS_BASE_ADDR + DDRC_PWRCTL); in imx_ddrc_enter_self_refresh()
531 writel(0x20, DDRC_IPS_BASE_ADDR + DDRC_PWRCTL); in imx_ddrc_enter_self_refresh()
534 writel(readl(DDRC_IPS_BASE_ADDR + DDRC_PWRCTL) | 0x8, in imx_ddrc_enter_self_refresh()
535 DDRC_IPS_BASE_ADDR + DDRC_PWRCTL); in imx_ddrc_enter_self_refresh()
540 writel(0, DDRC_IPS_BASE_ADDR + DDRC_PWRCTL); in imx_ddrc_exit_self_refresh()
543 writel(readl(DDRC_IPS_BASE_ADDR + DDRC_PWRCTL) | 0x1, in imx_ddrc_exit_self_refresh()
544 DDRC_IPS_BASE_ADDR + DDRC_PWRCTL); in imx_ddrc_exit_self_refresh()
/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c18 { DDRC_PWRCTL(0), 0x00000001 },
H A Dlpddr4_timing.c16 { DDRC_PWRCTL(0), 0x00000001 },
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h369 #define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30) macro