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Searched refs:DDRC_PERFWR1 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c113 { DDRC_PERFWR1(0), 0x1000012c },
H A Dlpddr4_timing.c76 { DDRC_PERFWR1(0), 0x02005574 },
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h470 #define DDRC_PERFWR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x26c) macro