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Searched refs:DDRC_PERFLPR1 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c111 { DDRC_PERFLPR1(0), 0x90000096 },
H A Dlpddr4_timing.c75 { DDRC_PERFLPR1(0), 0x00000009 },
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h469 #define DDRC_PERFLPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x264) macro