DDRC_PCTRL_0 (reference) in projects: openbmc

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Searched refs:DDRC_PCTRL_0 (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A D	ddr4_init.c	`107 reg32_write(DDRC_PCTRL_0(0), 0x00000001); in ddr_init()`
H A D	lpddr4_init.c	`183 reg32_write(DDRC_PCTRL_0(0), 0x00000001); in ddr_init()`
/openbmc/u-boot/board/freescale/imx8mq_evk/
H A D	lpddr4_timing_b0.c	`122 { DDRC_PCTRL_0(0), 0x00000001 },`
H A D	lpddr4_timing.c	`85 { DDRC_PCTRL_0(0), 0x00000001 },`
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A D	ddr.h	`517 #define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490) macro`

Last Index Update: Wed Jul 10 03:06:23 CDT 2024