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Searched refs:DDRC_PCFGW_0 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c121 { DDRC_PCFGW_0(0), 0x000072ff },
H A Dlpddr4_timing.c84 { DDRC_PCFGW_0(0), 0x000072ff },
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h510 #define DDRC_PCFGW_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x408) macro