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Searched refs:DDRC_MSTR (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c19 { DDRC_MSTR(0), 0xa3080020 },
H A Dlpddr4_timing.c17 { DDRC_MSTR(0), 0xa3080020 },
/openbmc/u-boot/board/toradex/colibri_imx7/
H A Dimximage.cfg51 /* DDRC_MSTR */
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h359 #define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00) macro