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Searched refs:DDRC_MRCTRL0 (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A Dddrphy_utils.c161 reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4)); in lpddr4_mr_write()
163 reg32setbit(DDRC_MRCTRL0(0), 31); in lpddr4_mr_write()
175 reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1); in lpddr4_mr_read()
177 reg32setbit(DDRC_MRCTRL0(0), 31); in lpddr4_mr_read()
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h362 #define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10) macro