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Searched refs:DDRC_FREQ2_INIT6 (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing.c129 { DDRC_FREQ2_INIT6(0), 0x0066004a },
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h572 #define DDRC_FREQ2_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e8) macro