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Searched refs:DDRC_FREQ1_RFSHTMG (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c82 { DDRC_FREQ1_RFSHTMG(0), 0x014001E },
132 { DDRC_FREQ1_RFSHTMG(0), 0x00610090 },
H A Dlpddr4_timing.c106 { DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h536 #define DDRC_FREQ1_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2064) macro