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Searched refs:DDRC_FREQ1_DRAMTMG5 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c92 { DDRC_FREQ1_DRAMTMG5(0), 0x2030303 },
H A Dlpddr4_timing.c97 { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h546 #define DDRC_FREQ1_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x2114) macro