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Searched refs:DDRC_FREQ1_DRAMTMG17 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c98 { DDRC_FREQ1_DRAMTMG17(0), 0x0220011 },
H A Dlpddr4_timing.c102 { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h558 #define DDRC_FREQ1_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x2144) macro