Home
last modified time | relevance | path

Searched refs:DDRC_FREQ1_DRAMTMG13 (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c96 { DDRC_FREQ1_DRAMTMG13(0), 0xA100002 },
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h554 #define DDRC_FREQ1_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x2134) macro