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Searched refs:DDRC_FREQ1_DRAMTMG1 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c88 { DDRC_FREQ1_DRAMTMG1(0), 0x003040A },
H A Dlpddr4_timing.c93 { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h542 #define DDRC_FREQ1_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2104) macro