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Searched refs:DDRC_DRAMTMG3 (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c35 { DDRC_DRAMTMG3(0), 0x00C0C000 },
H A Dlpddr4_timing.c33 { DDRC_DRAMTMG3(0), 0x00C0C000 },
/openbmc/u-boot/board/toradex/colibri_imx7/
H A Dimximage.cfg81 /* DDRC_DRAMTMG3 */
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h416 #define DDRC_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x10c) macro