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Searched refs:DDRC_DRAMTMG17 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c43 { DDRC_DRAMTMG17(0), 0x00A00050 },
H A Dlpddr4_timing.c41 { DDRC_DRAMTMG17(0), 0x00A00050 },
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h430 #define DDRC_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x144) macro