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Searched refs:DDRC_DRAMTMG14 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c42 { DDRC_DRAMTMG14(0), 0x000000E6 },
H A Dlpddr4_timing.c40 { DDRC_DRAMTMG14(0), 0x000000E6 },
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h427 #define DDRC_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x138) macro