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Searched refs:DDRC_DRAMTMG0 (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c33 { DDRC_DRAMTMG0(0), 0x1A201B22 },
H A Dlpddr4_timing.c31 { DDRC_DRAMTMG0(0), 0x1A201B22 },
/openbmc/u-boot/board/toradex/colibri_imx7/
H A Dimximage.cfg75 /* DDRC_DRAMTMG0 */
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h413 #define DDRC_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x100) macro