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Searched refs:DDRC_DFITMG1 (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c50 { DDRC_DFITMG1(0), 0x00080303 },
H A Dlpddr4_timing.c48 { DDRC_DFITMG1(0), 0x00080303 },
/openbmc/u-boot/board/toradex/colibri_imx7/
H A Dimximage.cfg95 /* DDRC_DFITMG1 */
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h436 #define DDRC_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x194) macro