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Searched refs:DDRC_DFIPHYMSTR (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A Dlpddr4_init.c172 reg32_write(DDRC_DFIPHYMSTR(0), 0x00000001); in ddr_init()
/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c58 { DDRC_DFIPHYMSTR(0), 0x00000001 },
H A Dlpddr4_timing.c56 { DDRC_DFIPHYMSTR(0), 0x00000001 },
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h447 #define DDRC_DFIPHYMSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c4) macro