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Searched refs:DDRC_DFIMISC (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A Dlpddr4_init.c98 reg32_write(DDRC_DFIMISC(0), 0x00000210); in ddr_init()
100 reg32_write(DDRC_DFIMISC(0), 0x00000110); in ddr_init()
102 reg32_write(DDRC_DFIMISC(0), 0x00000010); in ddr_init()
128 reg32_write(DDRC_DFIMISC(0), 0x00000230); in ddr_init()
130 reg32_write(DDRC_DFIMISC(0), 0x00000130); in ddr_init()
132 reg32_write(DDRC_DFIMISC(0), 0x00000030); in ddr_init()
147 reg32_write(DDRC_DFIMISC(0), 0x00000210); in ddr_init()
149 reg32_write(DDRC_DFIMISC(0), 0x00000211); in ddr_init()
151 reg32_write(DDRC_DFIMISC(0), 0x00000110); in ddr_init()
153 reg32_write(DDRC_DFIMISC(0), 0x00000111); in ddr_init()
[all …]
H A Dddr4_init.c71 reg32_write(DDRC_DFIMISC(0), 0x00000000); in ddr_init()
81 reg32_write(DDRC_DFIMISC(0), 0x00000020); in ddr_init()
88 reg32_write(DDRC_DFIMISC(0), 0x00000000); in ddr_init()
90 reg32_write(DDRC_DFIMISC(0), 0x00000001); in ddr_init()
/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c54 { DDRC_DFIMISC(0), 0x00000011 },
H A Dlpddr4_timing.c52 { DDRC_DFIMISC(0), 0x00000011 },
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h442 #define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0) macro