Searched refs:DDRC_DBG1 (Results 1 – 5 of 5) sorted by relevance
| /openbmc/u-boot/drivers/ddr/imx/imx8m/ |
| H A D | ddr4_init.c | 52 reg32_write(DDRC_DBG1(0), 0x00000001); in ddr_init()
67 reg32_write(DDRC_DBG1(0), 0x00000000); in ddr_init()
|
| H A D | lpddr4_init.c | 78 reg32_write(DDRC_DBG1(0), 0x00000000); in ddr_init()
|
| /openbmc/u-boot/board/freescale/imx8mq_evk/ |
| H A D | lpddr4_timing_b0.c | 16 { DDRC_DBG1(0), 0x00000001 },
115 { DDRC_DBG1(0), 0x00000000 },
|
| H A D | lpddr4_timing.c | 15 { DDRC_DBG1(0), 0x00000001 },
78 { DDRC_DBG1(0), 0x00000000 },
|
| /openbmc/u-boot/arch/arm/include/asm/arch-imx8m/ |
| H A D | ddr.h | 480 #define DDRC_DBG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x304) macro
|