Searched refs:DDR5 (Results 1 – 4 of 4) sorted by relevance
| /openbmc/bmcweb/redfish-core/include/generated/enums/ |
| H A D | processor.hpp | 49 DDR5, enumerator
135 {ProcessorMemoryType::DDR5, "DDR5"},
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| H A D | memory.hpp | 53 DDR5, enumerator
156 {MemoryDeviceType::DDR5, "DDR5"},
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| /openbmc/linux/Documentation/admin-guide/perf/ |
| H A D | alibaba_pmu.rst | 12 Yitian 710 employs eight DDR5/4 channels, four on each die. Each DDR5 channel
13 is independent of others to service system memory requests. And one DDR5
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| /openbmc/smbios-mdr/include/ |
| H A D | dimm.hpp | 231 {0x22, DeviceType::DDR5}, {0x23, DeviceType::LPDDR5_SDRAM}};
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