Searched refs:DDR5 (Results 1 – 5 of 5) sorted by relevance
| /openbmc/bmcweb/redfish-core/include/generated/enums/ |
| H A D | processor.hpp | 47 DDR5, enumerator
133 {ProcessorMemoryType::DDR5, "DDR5"},
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| H A D | memory.hpp | 51 DDR5, enumerator
154 {MemoryDeviceType::DDR5, "DDR5"},
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| /openbmc/linux/Documentation/admin-guide/perf/ |
| H A D | alibaba_pmu.rst | 12 Yitian 710 employs eight DDR5/4 channels, four on each die. Each DDR5 channel
13 is independent of others to service system memory requests. And one DDR5
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| /openbmc/smbios-mdr/include/ |
| H A D | dimm.hpp | 225 {0x22, DeviceType::DDR5}, {0x23, DeviceType::LPDDR5_SDRAM}};
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| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Inventory/Item/ |
| H A D | Dimm.interface.yaml | 229 - name: DDR5
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