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Searched refs:DDR3A_PLL (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/board/ti/ks2_evm/
H A Dboard_k2g.c162 [SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
163 [SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
164 [SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
165 [SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
169 [SYSCLK_19MHz] = {DDR3A_PLL, 194, 1, 14},
170 [SYSCLK_24MHz] = {DDR3A_PLL, 156, 1, 14},
171 [SYSCLK_25MHz] = {DDR3A_PLL, 149, 1, 14},
172 [SYSCLK_26MHz] = {DDR3A_PLL, 144, 1, 14},
/openbmc/u-boot/arch/arm/mach-keystone/include/mach/
H A Dclock.h31 #define DDR3_PLL DDR3A_PLL
85 DDR3A_PLL, enumerator
/openbmc/u-boot/arch/arm/mach-keystone/
H A Dclock.c31 [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
311 case DDR3A_PLL: in pll_freq_get()
359 freq = pll_freq_get(DDR3A_PLL); in ks_clk_get_rate()
H A Dcmd_clock.c35 cmd_pll_data.pll = DDR3A_PLL; in do_pll_cmd()