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Searched refs:DDR2_CONF_REG_VAL (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/arch/mips/mach-ath79/qca953x/
H A Dddr.c52 #define DDR2_CONF_REG_VAL (DDR_TRAS(27) | DDR_TRCD(9) | \ macro
324 writel(DDR2_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG); in ddr_init()