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Searched refs:DC_LOG_HW_LINK_TRAINING (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training.c198 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n", in dp_initialize_scrambling_data_symbols()
277 DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n", in dp_wait_for_training_aux_rd_interval()
604 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n" in dp_get_lane_status_and_lane_adjust()
614 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n" in dp_get_lane_status_and_lane_adjust()
1028 DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n", in dpcd_set_training_pattern()
1132 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n" in dpcd_set_lane_settings()
1191 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n", in dpcd_set_lt_pattern_and_lane_settings()
1210 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n" in dpcd_set_lt_pattern_and_lane_settings()
1218 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n" in dpcd_set_lt_pattern_and_lane_settings()
1281 DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n", in start_clock_recovery_pattern_early()
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H A Dlink_dp_training_dpia.c109 DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) configuring\n - LTTPR mode(%d)\n", in dpia_configure_link()
254 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n", in dpcd_set_lt_pattern()
260 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n", in dpcd_set_lt_pattern()
404 DC_LOG_HW_LINK_TRAINING("%s: Clock recovery OK\n", __func__); in dpia_training_cr_non_transparent()
437 DC_LOG_HW_LINK_TRAINING( in dpia_training_cr_non_transparent()
512 DC_LOG_HW_LINK_TRAINING("%s: Clock recovery OK\n", __func__); in dpia_training_cr_transparent()
544 DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) clock recovery\n -hop(%d)\n - result(%d)\n - retries(%d)\n", in dpia_training_cr_transparent()
738 DC_LOG_HW_LINK_TRAINING( in dpia_training_eq_non_transparent()
829 DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) equalization\n - hop(%d)\n - result(%d)\n - retries(%d)\n", in dpia_training_eq_transparent()
945 DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) end\n - hop(%d)\n - result(%d)\n - LTTPR mode(%d)\n", in dpia_training_end()
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H A Dlink_dp_training_128b_132b.c48 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X TX_FFE_PRESET_VALUE = %x\n", in dpcd_128b_132b_set_lane_settings()
217 DC_LOG_HW_LINK_TRAINING("%s: Channel EQ done.\n", __func__); in dp_perform_128b_132b_link_training()
223 DC_LOG_HW_LINK_TRAINING("%s: CDS done.\n", __func__); in dp_perform_128b_132b_link_training()
H A Dlink_dp_training_8b_10b.c229 DC_LOG_HW_LINK_TRAINING("%s: Clock recovery OK\n", __func__); in perform_8b_10b_clock_recovery_sequence()
392 DC_LOG_HW_LINK_TRAINING("%s: Channel EQ done.\n", __func__); in dp_perform_8b_10b_link_training()
415 DC_LOG_HW_LINK_TRAINING("%s: Channel EQ done.\n", __func__); in dp_perform_8b_10b_link_training()
H A Dlink_dp_training_fixed_vs_pe_retimer.c286 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n", in dp_perform_fixed_vs_pe_training_sequence_legacy()
632 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n", in dp_perform_fixed_vs_pe_training_sequence()
H A Dlink_dp_capability.c2114 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane count %d max_link rate %d \n", in dp_get_max_link_cap()
/openbmc/linux/drivers/gpu/drm/amd/display/include/
H A Dlogger_types.h43 #define DC_LOG_HW_LINK_TRAINING(...) pr_debug("[HW_LINK_TRAINING]:"__VA_ARGS__) macro