Home
last modified time | relevance | path

Searched refs:DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h4346 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x00000018 macro
H A Ddce_8_0_sh_mask.h6730 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18 macro
H A Ddce_10_0_sh_mask.h16015 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18 macro
H A Ddce_11_0_sh_mask.h16235 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18 macro
H A Ddce_11_2_sh_mask.h16985 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18 macro
H A Ddce_12_0_sh_mask.h7655 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_1_0_sh_mask.h32995 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT … macro
H A Ddcn_1_0_sh_mask.h27073 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h39328 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h43909 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h42011 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h44968 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h34999 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h31022 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h36335 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h35400 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h39325 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT … macro