Home
last modified time | relevance | path

Searched refs:DCSR31 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/dma/
H A Dpxa2xx_dma.c65 #define DCSR31 0x007c /* DMA Control / Status register for Channel 31 */ macro
291 case DCSR0 ... DCSR31: in pxa2xx_dma_read()
359 case DCSR0 ... DCSR31: in pxa2xx_dma_write()
/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h128 #define DCSR31 0x4000007c /* DMA Control / Status Register for Channel 31 */ macro