1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_ 14 #define ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_ 15 16 /* 17 ***************************************** 18 * DCORE0_HMMU0_STLB 19 * (Prototype: STLB) 20 ***************************************** 21 */ 22 23 /* DCORE0_HMMU0_STLB_BUSY */ 24 #define DCORE0_HMMU0_STLB_BUSY_BUSY_SHIFT 0 25 #define DCORE0_HMMU0_STLB_BUSY_BUSY_MASK 0xFFFFFFFF 26 27 /* DCORE0_HMMU0_STLB_ASID */ 28 #define DCORE0_HMMU0_STLB_ASID_ASID_SHIFT 0 29 #define DCORE0_HMMU0_STLB_ASID_ASID_MASK 0x3FF 30 31 /* DCORE0_HMMU0_STLB_HOP0_PA43_12 */ 32 #define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_SHIFT 0 33 #define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_MASK 0xFFFFFFFF 34 35 /* DCORE0_HMMU0_STLB_HOP0_PA63_44 */ 36 #define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_SHIFT 0 37 #define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_MASK 0xFFFFF 38 39 /* DCORE0_HMMU0_STLB_CACHE_INV */ 40 #define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0 41 #define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF 42 #define DCORE0_HMMU0_STLB_CACHE_INV_INDEX_MASK_SHIFT 8 43 #define DCORE0_HMMU0_STLB_CACHE_INV_INDEX_MASK_MASK 0xFF00 44 45 /* DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8 */ 46 #define DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8_PA_SHIFT 0 47 #define DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8_PA_MASK 0xFFFFFFFF 48 49 /* DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40 */ 50 #define DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40_PA_SHIFT 0 51 #define DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40_PA_MASK 0xFFFFFF 52 53 /* DCORE0_HMMU0_STLB_STLB_FEATURE_EN */ 54 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_SHIFT 0 55 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_MASK 0x1 56 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_SHIFT 1 57 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_MASK 0x2 58 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_LOOKUP_EN_SHIFT 2 59 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_LOOKUP_EN_MASK 0x4 60 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BYPASS_SHIFT 3 61 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BYPASS_MASK 0x8 62 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BANK_STOP_SHIFT 4 63 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BANK_STOP_MASK 0x10 64 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_TRACE_EN_SHIFT 5 65 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_TRACE_EN_MASK 0x20 66 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWER_EN_SHIFT 6 67 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK 0x40 68 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_CACHING_EN_SHIFT 7 69 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_CACHING_EN_MASK 0x1F80 70 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_SHIFT 13 71 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_MASK 0xE000 72 73 /* DCORE0_HMMU0_STLB_STLB_AXI_CACHE */ 74 #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_SHIFT 0 75 #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_MASK 0xF 76 #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_SHIFT 4 77 #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_MASK 0xF0 78 #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_INV_ARCACHE_SHIFT 8 79 #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_INV_ARCACHE_MASK 0xF00 80 81 /* DCORE0_HMMU0_STLB_HOP_CONFIGURATION */ 82 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_HOP_SHIFT 0 83 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_HOP_MASK 0x7 84 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_SHIFT 4 85 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_MASK 0x70 86 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_SHIFT 8 87 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_MASK 0x700 88 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LAST_HOP_SHIFT 12 89 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LAST_HOP_MASK 0x7000 90 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_SHIFT 16 91 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_MASK 0x70000 92 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_SHIFT 20 93 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_MASK 0x100000 94 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_SHIFT 21 95 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_MASK 0x7E00000 96 97 /* DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32 */ 98 #define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_SHIFT 0 99 #define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_MASK 0xFFFFFFFF 100 101 /* DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0 */ 102 #define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_SHIFT 0 103 #define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_MASK 0xFFFFFFFF 104 105 /* DCORE0_HMMU0_STLB_INV_ALL_START */ 106 #define DCORE0_HMMU0_STLB_INV_ALL_START_R_SHIFT 0 107 #define DCORE0_HMMU0_STLB_INV_ALL_START_R_MASK 0x1 108 109 /* DCORE0_HMMU0_STLB_INV_ALL_SET */ 110 #define DCORE0_HMMU0_STLB_INV_ALL_SET_R_SHIFT 0 111 #define DCORE0_HMMU0_STLB_INV_ALL_SET_R_MASK 0xFF 112 113 /* DCORE0_HMMU0_STLB_INV_PS */ 114 #define DCORE0_HMMU0_STLB_INV_PS_R_SHIFT 0 115 #define DCORE0_HMMU0_STLB_INV_PS_R_MASK 0x3 116 117 /* DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX */ 118 #define DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX_R_SHIFT 0 119 #define DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX_R_MASK 0xFF 120 121 /* DCORE0_HMMU0_STLB_INV_HIT_COUNT */ 122 #define DCORE0_HMMU0_STLB_INV_HIT_COUNT_R_SHIFT 0 123 #define DCORE0_HMMU0_STLB_INV_HIT_COUNT_R_MASK 0x7FF 124 125 /* DCORE0_HMMU0_STLB_INV_SET */ 126 #define DCORE0_HMMU0_STLB_INV_SET_R_SHIFT 0 127 #define DCORE0_HMMU0_STLB_INV_SET_R_MASK 0xFF 128 129 /* DCORE0_HMMU0_STLB_SRAM_INIT */ 130 #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_TAG_SHIFT 0 131 #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_TAG_MASK 0x3 132 #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_SLICE_SHIFT 2 133 #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_SLICE_MASK 0xC 134 #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_DATA_SHIFT 4 135 #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_DATA_MASK 0x10 136 137 /* DCORE0_HMMU0_STLB_MEM_CACHE_INVALIDATION */ 138 139 /* DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS */ 140 #define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_SHIFT 0 141 #define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_MASK 0x1 142 #define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_SHIFT 1 143 #define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_MASK 0x2 144 145 /* DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7 */ 146 #define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7_R_SHIFT 0 147 #define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7_R_MASK 0xFFFFFFFF 148 149 /* DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39 */ 150 #define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39_R_SHIFT 0 151 #define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39_R_MASK 0x1FFFFFF 152 153 /* DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG */ 154 #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_SHIFT 0 155 #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_MASK 0x3F 156 #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_SHIFT 6 157 #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_MASK 0xFC0 158 #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_BYPASS_EN_SHIFT 12 159 #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_BYPASS_EN_MASK 0x1000 160 #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_SHIFT 13 161 #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_MASK 0x2000 162 163 /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5 */ 164 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MIN_SHIFT 0 165 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MIN_MASK 0x1FF 166 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MAX_SHIFT 9 167 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MAX_MASK 0x3FE00 168 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MASK_SHIFT 18 169 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MASK_MASK 0x7FC0000 170 171 /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4 */ 172 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MIN_SHIFT 0 173 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MIN_MASK 0x1FF 174 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MAX_SHIFT 9 175 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MAX_MASK 0x3FE00 176 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MASK_SHIFT 18 177 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MASK_MASK 0x7FC0000 178 179 /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3 */ 180 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MIN_SHIFT 0 181 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MIN_MASK 0x1FF 182 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MAX_SHIFT 9 183 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MAX_MASK 0x3FE00 184 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MASK_SHIFT 18 185 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MASK_MASK 0x7FC0000 186 187 /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2 */ 188 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MIN_SHIFT 0 189 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MIN_MASK 0x1FF 190 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MAX_SHIFT 9 191 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MAX_MASK 0x3FE00 192 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MASK_SHIFT 18 193 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MASK_MASK 0x7FC0000 194 195 /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1 */ 196 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MIN_SHIFT 0 197 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MIN_MASK 0x1FF 198 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MAX_SHIFT 9 199 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MAX_MASK 0x3FE00 200 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MASK_SHIFT 18 201 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MASK_MASK 0x7FC0000 202 203 /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0 */ 204 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MIN_SHIFT 0 205 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MIN_MASK 0x1FF 206 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MAX_SHIFT 9 207 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MAX_MASK 0x3FE00 208 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MASK_SHIFT 18 209 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MASK_MASK 0x7FC0000 210 211 /* DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_CLR */ 212 213 /* DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK */ 214 #define DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK_R_SHIFT 0 215 #define DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK_R_MASK 0x1 216 217 /* DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG */ 218 #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_SHIFT 0 219 #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_MASK 0x1 220 #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_SHIFT 1 221 #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_MASK 0x2 222 #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_SHIFT 2 223 #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_MASK 0x4 224 225 /* DCORE0_HMMU0_STLB_MEM_READ_ARPROT */ 226 #define DCORE0_HMMU0_STLB_MEM_READ_ARPROT_R_SHIFT 0 227 #define DCORE0_HMMU0_STLB_MEM_READ_ARPROT_R_MASK 0x7 228 229 /* DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION */ 230 #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_SHIFT 0 231 #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_MASK 0x1 232 #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_SHIFT 1 233 #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_MASK 0x2 234 #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_SHIFT 2 235 #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_MASK 0xFFC 236 237 /* DCORE0_HMMU0_STLB_RANGE_INV_START_LSB */ 238 #define DCORE0_HMMU0_STLB_RANGE_INV_START_LSB_INV_START_LSB_SHIFT 0 239 #define DCORE0_HMMU0_STLB_RANGE_INV_START_LSB_INV_START_LSB_MASK 0xFFFFFFFF 240 241 /* DCORE0_HMMU0_STLB_RANGE_INV_START_MSB */ 242 #define DCORE0_HMMU0_STLB_RANGE_INV_START_MSB_INV_START_MSB_SHIFT 0 243 #define DCORE0_HMMU0_STLB_RANGE_INV_START_MSB_INV_START_MSB_MASK 0xFFFFF 244 245 /* DCORE0_HMMU0_STLB_RANGE_INV_END_LSB */ 246 #define DCORE0_HMMU0_STLB_RANGE_INV_END_LSB_INV_END_LSB_SHIFT 0 247 #define DCORE0_HMMU0_STLB_RANGE_INV_END_LSB_INV_END_LSB_MASK 0xFFFFFFFF 248 249 /* DCORE0_HMMU0_STLB_RANGE_INV_END_MSB */ 250 #define DCORE0_HMMU0_STLB_RANGE_INV_END_MSB_INV_END_MSB_SHIFT 0 251 #define DCORE0_HMMU0_STLB_RANGE_INV_END_MSB_INV_END_MSB_MASK 0xFFFFF 252 253 /* DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL */ 254 #define DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_SHIFT 0 255 #define DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_MASK 0x1 256 257 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0 */ 258 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_SHIFT 0 259 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_MASK 0x1FF 260 261 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1 */ 262 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_SHIFT 0 263 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_MASK 0x1FF 264 265 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2 */ 266 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_SHIFT 0 267 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_MASK 0x1FF 268 269 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3 */ 270 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_SHIFT 0 271 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_MASK 0x1FF 272 273 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4 */ 274 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_SHIFT 0 275 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_MASK 0x1FF 276 277 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5 */ 278 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_SHIFT 0 279 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_MASK 0x1FF 280 281 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6 */ 282 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_SHIFT 0 283 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_MASK 0x1FF 284 285 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7 */ 286 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_SHIFT 0 287 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_MASK 0x1FF 288 289 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8 */ 290 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_SHIFT 0 291 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_MASK 0x1FF 292 293 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9 */ 294 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_SHIFT 0 295 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_MASK 0x1FF 296 297 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10 */ 298 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_SHIFT 0 299 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_MASK 0x1FF 300 301 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11 */ 302 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_SHIFT 0 303 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_MASK 0x1FF 304 305 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12 */ 306 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_SHIFT 0 307 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_MASK 0x1FF 308 309 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13 */ 310 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_SHIFT 0 311 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_MASK 0x1FF 312 313 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14 */ 314 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_SHIFT 0 315 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_MASK 0x1FF 316 317 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15 */ 318 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_SHIFT 0 319 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_MASK 0x1FF 320 321 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16 */ 322 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_SHIFT 0 323 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_MASK 0x1FF 324 325 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17 */ 326 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_SHIFT 0 327 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_MASK 0x1FF 328 329 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18 */ 330 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_SHIFT 0 331 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_MASK 0x1FF 332 333 #endif /* ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_ */ 334