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Searched refs:DB_COUNT_CONTROL__SFAIL_ENABLE_MASK (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h3230 #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000f0000L macro
H A Dgfx_7_2_sh_mask.h3543 #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000 macro
H A Dgfx_8_0_sh_mask.h4267 #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000 macro
H A Dgfx_8_1_sh_mask.h4789 #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h14375 #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h15544 #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h15682 #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK … macro
H A Dgc_9_4_3_sh_mask.h17847 #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK … macro
H A Dgc_9_4_2_sh_mask.h7799 #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h19351 #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h21681 #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h21774 #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h19878 #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK … macro