1 /*
2  * DCE_11_2 Register documentation
3  *
4  * Copyright (C) 2016  Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included
14  * in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22  */
23 
24 #ifndef DCE_11_2_ENUM_H
25 #define DCE_11_2_ENUM_H
26 
27 typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL {
28 	CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL        = 0x0,
29 	CRTC_CONTROL_CRTC_START_POINT_CNTL_DP            = 0x1,
30 } CRTC_CONTROL_CRTC_START_POINT_CNTL;
31 typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL {
32 	CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL       = 0x0,
33 	CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP           = 0x1,
34 } CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL;
35 typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL {
36 	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE     = 0x0,
37 	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT= 0x1,
38 	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED    = 0x2,
39 	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST= 0x3,
40 } CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL;
41 typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY {
42 	CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE    = 0x0,
43 	CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE     = 0x1,
44 } CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY;
45 typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE {
46 	CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE= 0x0,
47 	CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 0x1,
48 } CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE;
49 typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN {
50 	CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE              = 0x0,
51 	CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE               = 0x1,
52 } CRTC_CONTROL_CRTC_SOF_PULL_EN;
53 typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL {
54 	CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE       = 0x0,
55 	CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE        = 0x1,
56 } CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL;
57 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL {
58 	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE  = 0x0,
59 	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE   = 0x1,
60 } CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL;
61 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL {
62 	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE  = 0x0,
63 	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE   = 0x1,
64 } CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL;
65 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN {
66 	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE= 0x0,
67 	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE= 0x1,
68 } CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN;
69 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC {
70 	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE= 0x0,
71 	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE= 0x1,
72 } CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC;
73 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT {
74 	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE= 0x0,
75 	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE= 0x1,
76 } CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT;
77 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK {
78 	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_FRAME_START= 0x0,
79 	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_A= 0x1,
80 	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_B= 0x2,
81 	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CURSOR_CHANGE= 0x3,
82 	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_OTHER_CLIENT= 0x4,
83 	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION0= 0x5,
84 	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION1= 0x6,
85 	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION2= 0x7,
86 	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION3= 0x8,
87 	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_GRAPHIC_UPDATE_PENDING= 0x9,
88 	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED2= 0xa,
89 	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_INVALID= 0xb,
90 	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_DOUBLE_BUFFER= 0xc,
91 	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT_NOM= 0xd,
92 	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT= 0xe,
93 	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED= 0xf,
94 } CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK;
95 typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
96 	CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE= 0x0,
97 	CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE= 0x1,
98 } CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK;
99 typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR {
100 	CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE= 0x0,
101 	CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE= 0x1,
102 } CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR;
103 typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL {
104 	CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE       = 0x0,
105 	CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE        = 0x1,
106 } CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL;
107 typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN {
108 	CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE     = 0x0,
109 	CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE      = 0x1,
110 } CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN;
111 typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT {
112 	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER= 0x1,
113 	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER= 0x2,
114 	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF= 0x5,
115 	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE= 0x6,
116 	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA  = 0x7,
117 	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA  = 0x8,
118 	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB  = 0x9,
119 	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB  = 0xa,
120 	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1    = 0xb,
121 	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2    = 0xc,
122 	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD= 0xd,
123 	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC= 0xe,
124 	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0   = 0x10,
125 	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1   = 0x11,
126 	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2   = 0x12,
127 	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON   = 0x13,
128 	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA= 0x14,
129 	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB= 0x15,
130 	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW= 0x16,
131 	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW= 0x17,
132 } CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT;
133 typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT {
134 	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE= 0x1,
135 	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA= 0x2,
136 	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB= 0x3,
137 	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA= 0x4,
138 	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB= 0x5,
139 	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO = 0x6,
140 	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC= 0x7,
141 } CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT;
142 typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN {
143 	CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE= 0x0,
144 	CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x1,
145 } CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN;
146 typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR {
147 	CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE           = 0x0,
148 	CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE            = 0x1,
149 } CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR;
150 typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT {
151 	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER= 0x1,
152 	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER= 0x2,
153 	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF= 0x5,
154 	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE= 0x6,
155 	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA  = 0x7,
156 	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA  = 0x8,
157 	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB  = 0x9,
158 	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB  = 0xa,
159 	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1    = 0xb,
160 	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2    = 0xc,
161 	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD= 0xd,
162 	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC= 0xe,
163 	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0   = 0x10,
164 	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1   = 0x11,
165 	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2   = 0x12,
166 	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON   = 0x13,
167 	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA= 0x14,
168 	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB= 0x15,
169 	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW= 0x16,
170 	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW= 0x17,
171 } CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT;
172 typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT {
173 	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE= 0x1,
174 	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA= 0x2,
175 	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB= 0x3,
176 	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA= 0x4,
177 	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB= 0x5,
178 	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO = 0x6,
179 	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC= 0x7,
180 } CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT;
181 typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN {
182 	CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE= 0x0,
183 	CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x1,
184 } CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN;
185 typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR {
186 	CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE           = 0x0,
187 	CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE            = 0x1,
188 } CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR;
189 typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE {
190 	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE= 0x0,
191 	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT= 0x1,
192 	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT= 0x2,
193 	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED= 0x3,
194 } CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE;
195 typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK {
196 	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE= 0x0,
197 	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE= 0x1,
198 } CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK;
199 typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL {
200 	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE= 0x0,
201 	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE= 0x1,
202 } CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL;
203 typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR {
204 	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE= 0x0,
205 	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE= 0x1,
206 } CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR;
207 typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT {
208 	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0= 0x0,
209 	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF= 0x1,
210 	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE= 0x2,
211 	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1= 0x3,
212 	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2= 0x4,
213 	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA= 0x5,
214 	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK= 0x6,
215 	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA= 0x7,
216 	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK= 0x8,
217 	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK= 0x9,
218 	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL= 0xa,
219 	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1= 0xb,
220 	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB= 0xc,
221 	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA= 0xd,
222 	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD= 0xe,
223 	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC= 0xf,
224 } CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT;
225 typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY {
226 	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE= 0x0,
227 	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE= 0x1,
228 } CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY;
229 typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY {
230 	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE= 0x0,
231 	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE= 0x1,
232 } CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY;
233 typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE {
234 	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO= 0x0,
235 	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT= 0x1,
236 	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT= 0x2,
237 	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED= 0x3,
238 } CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE;
239 typedef enum CRTC_CONTROL_CRTC_MASTER_EN {
240 	CRTC_CONTROL_CRTC_MASTER_EN_FALSE                = 0x0,
241 	CRTC_CONTROL_CRTC_MASTER_EN_TRUE                 = 0x1,
242 } CRTC_CONTROL_CRTC_MASTER_EN;
243 typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN {
244 	CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE      = 0x0,
245 	CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE       = 0x1,
246 } CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN;
247 typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE {
248 	CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE      = 0x0,
249 	CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE       = 0x1,
250 } CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE;
251 typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE {
252 	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE= 0x0,
253 	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE= 0x1,
254 } CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE;
255 typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD {
256 	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT= 0x0,
257 	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD= 0x1,
258 	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN= 0x2,
259 	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2= 0x3,
260 } CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD;
261 typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY {
262 	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE= 0x0,
263 	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE= 0x1,
264 } CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY;
265 typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT {
266 	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE= 0x0,
267 	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE= 0x1,
268 } CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT;
269 typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN {
270 	CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE  = 0x0,
271 	CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE   = 0x1,
272 } CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN;
273 typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE {
274 	CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE= 0x0,
275 	CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE= 0x1,
276 } CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE;
277 typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR {
278 	CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE= 0x0,
279 	CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE= 0x1,
280 } CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR;
281 typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE {
282 	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE= 0x0,
283 	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA= 0x1,
284 	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB= 0x2,
285 	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED= 0x3,
286 } CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE;
287 typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY {
288 	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE= 0x0,
289 	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE= 0x1,
290 } CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY;
291 typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY {
292 	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE= 0x0,
293 	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE= 0x1,
294 } CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY;
295 typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY {
296 	CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE= 0x0,
297 	CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE= 0x1,
298 } CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY;
299 typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN {
300 	CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE         = 0x0,
301 	CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE          = 0x1,
302 } CRTC_STEREO_CONTROL_CRTC_STEREO_EN;
303 typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR {
304 	CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE   = 0x0,
305 	CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE    = 0x1,
306 } CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR;
307 typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL {
308 	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE= 0x0,
309 	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA= 0x1,
310 	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB= 0x2,
311 	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED= 0x3,
312 } CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL;
313 typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY {
314 	CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE= 0x0,
315 	CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE= 0x1,
316 } CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY;
317 typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY {
318 	CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE= 0x0,
319 	CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE= 0x1,
320 } CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY;
321 typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN {
322 	CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE= 0x0,
323 	CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE= 0x1,
324 } CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN;
325 typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN {
326 	CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE   = 0x0,
327 	CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE    = 0x1,
328 } CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN;
329 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK {
330 	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE= 0x0,
331 	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE= 0x1,
332 } CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK;
333 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE {
334 	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE= 0x0,
335 	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE= 0x1,
336 } CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE;
337 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK {
338 	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE= 0x0,
339 	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE= 0x1,
340 } CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK;
341 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE {
342 	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE= 0x0,
343 	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE= 0x1,
344 } CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE;
345 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK {
346 	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE= 0x0,
347 	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE= 0x1,
348 } CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK;
349 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE {
350 	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE= 0x0,
351 	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE= 0x1,
352 } CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE;
353 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK {
354 	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE= 0x0,
355 	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE= 0x1,
356 } CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK;
357 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
358 	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE= 0x0,
359 	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE= 0x1,
360 } CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
361 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK {
362 	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE  = 0x0,
363 	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE   = 0x1,
364 } CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK;
365 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE {
366 	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE = 0x0,
367 	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE  = 0x1,
368 } CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE;
369 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK {
370 	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE  = 0x0,
371 	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE   = 0x1,
372 } CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK;
373 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE {
374 	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE = 0x0,
375 	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE  = 0x1,
376 } CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE;
377 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK {
378 	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE= 0x0,
379 	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE= 0x1,
380 } CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK;
381 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE {
382 	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE= 0x0,
383 	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE= 0x1,
384 } CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE;
385 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK {
386 	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE= 0x0,
387 	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE= 0x1,
388 } CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK;
389 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE {
390 	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE= 0x0,
391 	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE= 0x1,
392 } CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE;
393 typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK {
394 	CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE          = 0x0,
395 	CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE           = 0x1,
396 } CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK;
397 typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY {
398 	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE= 0x0,
399 	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE= 0x1,
400 } CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY;
401 typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN {
402 	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE= 0x0,
403 	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE= 0x1,
404 } CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN;
405 typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE {
406 	CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE= 0x0,
407 	CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE= 0x1,
408 } CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE;
409 typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN {
410 	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE= 0x0,
411 	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE= 0x1,
412 } CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN;
413 typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE {
414 	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB= 0x0,
415 	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601= 0x1,
416 	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709= 0x2,
417 	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS= 0x3,
418 	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS= 0x4,
419 	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB= 0x5,
420 	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB= 0x6,
421 	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS= 0x7,
422 } CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE;
423 typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE {
424 	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE= 0x0,
425 	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE= 0x1,
426 } CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE;
427 typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT {
428 	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC= 0x0,
429 	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC= 0x1,
430 	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC= 0x2,
431 	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED= 0x3,
432 } CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT;
433 typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
434 	MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE      = 0x0,
435 	MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE       = 0x1,
436 } MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
437 typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK {
438 	MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE= 0x0,
439 	MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE= 0x1,
440 } MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK;
441 typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
442 	MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE   = 0x0,
443 	MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE    = 0x1,
444 } MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK;
445 typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE {
446 	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN    = 0x0,
447 	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA     = 0x1,
448 	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA     = 0x2,
449 	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE     = 0x3,
450 } MASTER_UPDATE_MODE_MASTER_UPDATE_MODE;
451 typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
452 	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH= 0x0,
453 	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN= 0x1,
454 	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD= 0x2,
455 	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED= 0x3,
456 } MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
457 typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE {
458 	CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE= 0x0,
459 	CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG= 0x1,
460 	CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL= 0x2,
461 } CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE;
462 typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR {
463 	CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE        = 0x0,
464 	CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE         = 0x1,
465 } CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR;
466 typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {
467 	CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE= 0x0,
468 	CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE= 0x1,
469 } CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR;
470 typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR {
471 	CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE= 0x0,
472 	CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE= 0x1,
473 } CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR;
474 typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
475 	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE= 0x0,
476 	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE= 0x1,
477 } CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
478 typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE {
479 	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE= 0x0,
480 	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE= 0x1,
481 } CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE;
482 typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR {
483 	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE= 0x0,
484 	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE= 0x1,
485 } CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR;
486 typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE {
487 	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE= 0x0,
488 	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE= 0x1,
489 } CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE;
490 typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR {
491 	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE= 0x0,
492 	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE= 0x1,
493 } CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR;
494 typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE {
495 	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE= 0x0,
496 	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE= 0x1,
497 } CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE;
498 typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE {
499 	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE= 0x0,
500 	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE= 0x1,
501 } CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE;
502 typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR {
503 	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE= 0x0,
504 	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE= 0x1,
505 } CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR;
506 typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE {
507 	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE= 0x0,
508 	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE= 0x1,
509 } CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE;
510 typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE {
511 	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE= 0x0,
512 	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE= 0x1,
513 } CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE;
514 typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN {
515 	CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE                  = 0x0,
516 	CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE                   = 0x1,
517 } CRTC_CRC_CNTL_CRTC_CRC_EN;
518 typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN {
519 	CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE             = 0x0,
520 	CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE              = 0x1,
521 } CRTC_CRC_CNTL_CRTC_CRC_CONT_EN;
522 typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE {
523 	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT          = 0x0,
524 	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT         = 0x1,
525 	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES     = 0x2,
526 	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS   = 0x3,
527 } CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE;
528 typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE {
529 	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP        = 0x0,
530 	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM     = 0x1,
531 	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM= 0x2,
532 	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD = 0x3,
533 } CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE;
534 typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS {
535 	CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE= 0x0,
536 	CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE= 0x1,
537 } CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS;
538 typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT {
539 	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB          = 0x0,
540 	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B         = 0x1,
541 	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB         = 0x2,
542 	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B        = 0x3,
543 	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB          = 0x4,
544 	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B         = 0x5,
545 	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB         = 0x6,
546 	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B        = 0x7,
547 } CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT;
548 typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT {
549 	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB          = 0x0,
550 	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B         = 0x1,
551 	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB         = 0x2,
552 	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B        = 0x3,
553 	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB          = 0x4,
554 	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B         = 0x5,
555 	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB         = 0x6,
556 	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B        = 0x7,
557 } CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT;
558 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE {
559 	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE= 0x0,
560 	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT= 0x1,
561 	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS= 0x2,
562 	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED= 0x3,
563 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE;
564 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE {
565 	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE= 0x0,
566 	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE= 0x1,
567 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE;
568 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE {
569 	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE= 0x0,
570 	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE= 0x1,
571 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE;
572 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW {
573 	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel= 0x0,
574 	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel= 0x1,
575 	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel= 0x2,
576 	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel= 0x3,
577 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW;
578 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE {
579 	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE= 0x0,
580 	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE= 0x1,
581 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE;
582 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE {
583 	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE= 0x0,
584 	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE= 0x1,
585 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE;
586 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY {
587 	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE= 0x0,
588 	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE= 0x1,
589 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY;
590 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY {
591 	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE= 0x0,
592 	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE= 0x1,
593 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY;
594 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE {
595 	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE= 0x0,
596 	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE= 0x1,
597 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE;
598 typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE {
599 	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE= 0x0,
600 	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE= 0x1,
601 } CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE;
602 typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR {
603 	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE= 0x0,
604 	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE= 0x1,
605 } CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR;
606 typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE {
607 	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE= 0x0,
608 	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE= 0x1,
609 } CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE;
610 typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT {
611 	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME= 0x0,
612 	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME= 0x1,
613 	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME= 0x2,
614 	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME= 0x3,
615 	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME= 0x4,
616 	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME= 0x5,
617 	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME= 0x6,
618 	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME= 0x7,
619 } CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT;
620 typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE {
621 	CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE= 0x0,
622 	CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE= 0x1,
623 } CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE;
624 typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR {
625 	CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE= 0x0,
626 	CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE= 0x1,
627 } CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR;
628 typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE {
629 	CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE= 0x0,
630 	CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE= 0x1,
631 } CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE;
632 typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE {
633 	CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE= 0x0,
634 	CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE= 0x1,
635 } CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE;
636 typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR {
637 	CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE= 0x0,
638 	CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE= 0x1,
639 } CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR;
640 typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE {
641 	CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE= 0x0,
642 	CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE= 0x1,
643 } CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE;
644 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE {
645 	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE= 0x0,
646 	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE= 0x1,
647 } CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE;
648 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR {
649 	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE= 0x0,
650 	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE= 0x1,
651 } CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR;
652 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE {
653 	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE= 0x0,
654 	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE= 0x1,
655 } CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE;
656 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE {
657 	CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE= 0x0,
658 	CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE= 0x1,
659 } CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE;
660 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE {
661 	CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF= 0x0,
662 	CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON= 0x1,
663 } CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE;
664 typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN {
665 	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE= 0x0,
666 	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE= 0x1,
667 } CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN;
668 typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB {
669 	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE= 0x0,
670 	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE= 0x1,
671 } CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB;
672 typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE {
673 	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH= 0x0,
674 	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE= 0x1,
675 	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE= 0x2,
676 	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED= 0x3,
677 } CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE;
678 typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR {
679 	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE= 0x0,
680 	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE= 0x1,
681 } CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR;
682 typedef enum CRTC_V_SYNC_A_POL {
683 	CRTC_V_SYNC_A_POL_HIGH                           = 0x0,
684 	CRTC_V_SYNC_A_POL_LOW                            = 0x1,
685 } CRTC_V_SYNC_A_POL;
686 typedef enum CRTC_H_SYNC_A_POL {
687 	CRTC_H_SYNC_A_POL_HIGH                           = 0x0,
688 	CRTC_H_SYNC_A_POL_LOW                            = 0x1,
689 } CRTC_H_SYNC_A_POL;
690 typedef enum CRTC_HORZ_REPETITION_COUNT {
691 	CRTC_HORZ_REPETITION_COUNT_0                     = 0x0,
692 	CRTC_HORZ_REPETITION_COUNT_1                     = 0x1,
693 	CRTC_HORZ_REPETITION_COUNT_2                     = 0x2,
694 	CRTC_HORZ_REPETITION_COUNT_3                     = 0x3,
695 	CRTC_HORZ_REPETITION_COUNT_4                     = 0x4,
696 	CRTC_HORZ_REPETITION_COUNT_5                     = 0x5,
697 	CRTC_HORZ_REPETITION_COUNT_6                     = 0x6,
698 	CRTC_HORZ_REPETITION_COUNT_7                     = 0x7,
699 	CRTC_HORZ_REPETITION_COUNT_8                     = 0x8,
700 	CRTC_HORZ_REPETITION_COUNT_9                     = 0x9,
701 	CRTC_HORZ_REPETITION_COUNT_10                    = 0xa,
702 	CRTC_HORZ_REPETITION_COUNT_11                    = 0xb,
703 	CRTC_HORZ_REPETITION_COUNT_12                    = 0xc,
704 	CRTC_HORZ_REPETITION_COUNT_13                    = 0xd,
705 	CRTC_HORZ_REPETITION_COUNT_14                    = 0xe,
706 	CRTC_HORZ_REPETITION_COUNT_15                    = 0xf,
707 } CRTC_HORZ_REPETITION_COUNT;
708 typedef enum PERFCOUNTER_CVALUE_SEL {
709 	PERFCOUNTER_CVALUE_SEL_47_0                      = 0x0,
710 	PERFCOUNTER_CVALUE_SEL_15_0                      = 0x1,
711 	PERFCOUNTER_CVALUE_SEL_31_16                     = 0x2,
712 	PERFCOUNTER_CVALUE_SEL_47_32                     = 0x3,
713 	PERFCOUNTER_CVALUE_SEL_11_0                      = 0x4,
714 	PERFCOUNTER_CVALUE_SEL_23_12                     = 0x5,
715 	PERFCOUNTER_CVALUE_SEL_35_24                     = 0x6,
716 	PERFCOUNTER_CVALUE_SEL_47_36                     = 0x7,
717 } PERFCOUNTER_CVALUE_SEL;
718 typedef enum PERFCOUNTER_INC_MODE {
719 	PERFCOUNTER_INC_MODE_MULTI_BIT                   = 0x0,
720 	PERFCOUNTER_INC_MODE_BOTH_EDGE                   = 0x1,
721 	PERFCOUNTER_INC_MODE_LSB                         = 0x2,
722 	PERFCOUNTER_INC_MODE_POS_EDGE                    = 0x3,
723 } PERFCOUNTER_INC_MODE;
724 typedef enum PERFCOUNTER_HW_CNTL_SEL {
725 	PERFCOUNTER_HW_CNTL_SEL_RUNEN                    = 0x0,
726 	PERFCOUNTER_HW_CNTL_SEL_CNTOFF                   = 0x1,
727 } PERFCOUNTER_HW_CNTL_SEL;
728 typedef enum PERFCOUNTER_RUNEN_MODE {
729 	PERFCOUNTER_RUNEN_MODE_LEVEL                     = 0x0,
730 	PERFCOUNTER_RUNEN_MODE_EDGE                      = 0x1,
731 } PERFCOUNTER_RUNEN_MODE;
732 typedef enum PERFCOUNTER_CNTOFF_START_DIS {
733 	PERFCOUNTER_CNTOFF_START_ENABLE                  = 0x0,
734 	PERFCOUNTER_CNTOFF_START_DISABLE                 = 0x1,
735 } PERFCOUNTER_CNTOFF_START_DIS;
736 typedef enum PERFCOUNTER_RESTART_EN {
737 	PERFCOUNTER_RESTART_DISABLE                      = 0x0,
738 	PERFCOUNTER_RESTART_ENABLE                       = 0x1,
739 } PERFCOUNTER_RESTART_EN;
740 typedef enum PERFCOUNTER_INT_EN {
741 	PERFCOUNTER_INT_DISABLE                          = 0x0,
742 	PERFCOUNTER_INT_ENABLE                           = 0x1,
743 } PERFCOUNTER_INT_EN;
744 typedef enum PERFCOUNTER_OFF_MASK {
745 	PERFCOUNTER_OFF_MASK_DISABLE                     = 0x0,
746 	PERFCOUNTER_OFF_MASK_ENABLE                      = 0x1,
747 } PERFCOUNTER_OFF_MASK;
748 typedef enum PERFCOUNTER_ACTIVE {
749 	PERFCOUNTER_IS_IDLE                              = 0x0,
750 	PERFCOUNTER_IS_ACTIVE                            = 0x1,
751 } PERFCOUNTER_ACTIVE;
752 typedef enum PERFCOUNTER_INT_TYPE {
753 	PERFCOUNTER_INT_TYPE_LEVEL                       = 0x0,
754 	PERFCOUNTER_INT_TYPE_PULSE                       = 0x1,
755 } PERFCOUNTER_INT_TYPE;
756 typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
757 	PERFCOUNTER_COUNTED_VALUE_TYPE_ACC               = 0x0,
758 	PERFCOUNTER_COUNTED_VALUE_TYPE_MAX               = 0x1,
759 } PERFCOUNTER_COUNTED_VALUE_TYPE;
760 typedef enum PERFCOUNTER_CNTL_SEL {
761 	PERFCOUNTER_CNTL_SEL_0                           = 0x0,
762 	PERFCOUNTER_CNTL_SEL_1                           = 0x1,
763 	PERFCOUNTER_CNTL_SEL_2                           = 0x2,
764 	PERFCOUNTER_CNTL_SEL_3                           = 0x3,
765 	PERFCOUNTER_CNTL_SEL_4                           = 0x4,
766 	PERFCOUNTER_CNTL_SEL_5                           = 0x5,
767 	PERFCOUNTER_CNTL_SEL_6                           = 0x6,
768 	PERFCOUNTER_CNTL_SEL_7                           = 0x7,
769 } PERFCOUNTER_CNTL_SEL;
770 typedef enum PERFCOUNTER_CNT0_STATE {
771 	PERFCOUNTER_CNT0_STATE_RESET                     = 0x0,
772 	PERFCOUNTER_CNT0_STATE_START                     = 0x1,
773 	PERFCOUNTER_CNT0_STATE_FREEZE                    = 0x2,
774 	PERFCOUNTER_CNT0_STATE_HW                        = 0x3,
775 } PERFCOUNTER_CNT0_STATE;
776 typedef enum PERFCOUNTER_STATE_SEL0 {
777 	PERFCOUNTER_STATE_SEL0_GLOBAL                    = 0x0,
778 	PERFCOUNTER_STATE_SEL0_LOCAL                     = 0x1,
779 } PERFCOUNTER_STATE_SEL0;
780 typedef enum PERFCOUNTER_CNT1_STATE {
781 	PERFCOUNTER_CNT1_STATE_RESET                     = 0x0,
782 	PERFCOUNTER_CNT1_STATE_START                     = 0x1,
783 	PERFCOUNTER_CNT1_STATE_FREEZE                    = 0x2,
784 	PERFCOUNTER_CNT1_STATE_HW                        = 0x3,
785 } PERFCOUNTER_CNT1_STATE;
786 typedef enum PERFCOUNTER_STATE_SEL1 {
787 	PERFCOUNTER_STATE_SEL1_GLOBAL                    = 0x0,
788 	PERFCOUNTER_STATE_SEL1_LOCAL                     = 0x1,
789 } PERFCOUNTER_STATE_SEL1;
790 typedef enum PERFCOUNTER_CNT2_STATE {
791 	PERFCOUNTER_CNT2_STATE_RESET                     = 0x0,
792 	PERFCOUNTER_CNT2_STATE_START                     = 0x1,
793 	PERFCOUNTER_CNT2_STATE_FREEZE                    = 0x2,
794 	PERFCOUNTER_CNT2_STATE_HW                        = 0x3,
795 } PERFCOUNTER_CNT2_STATE;
796 typedef enum PERFCOUNTER_STATE_SEL2 {
797 	PERFCOUNTER_STATE_SEL2_GLOBAL                    = 0x0,
798 	PERFCOUNTER_STATE_SEL2_LOCAL                     = 0x1,
799 } PERFCOUNTER_STATE_SEL2;
800 typedef enum PERFCOUNTER_CNT3_STATE {
801 	PERFCOUNTER_CNT3_STATE_RESET                     = 0x0,
802 	PERFCOUNTER_CNT3_STATE_START                     = 0x1,
803 	PERFCOUNTER_CNT3_STATE_FREEZE                    = 0x2,
804 	PERFCOUNTER_CNT3_STATE_HW                        = 0x3,
805 } PERFCOUNTER_CNT3_STATE;
806 typedef enum PERFCOUNTER_STATE_SEL3 {
807 	PERFCOUNTER_STATE_SEL3_GLOBAL                    = 0x0,
808 	PERFCOUNTER_STATE_SEL3_LOCAL                     = 0x1,
809 } PERFCOUNTER_STATE_SEL3;
810 typedef enum PERFCOUNTER_CNT4_STATE {
811 	PERFCOUNTER_CNT4_STATE_RESET                     = 0x0,
812 	PERFCOUNTER_CNT4_STATE_START                     = 0x1,
813 	PERFCOUNTER_CNT4_STATE_FREEZE                    = 0x2,
814 	PERFCOUNTER_CNT4_STATE_HW                        = 0x3,
815 } PERFCOUNTER_CNT4_STATE;
816 typedef enum PERFCOUNTER_STATE_SEL4 {
817 	PERFCOUNTER_STATE_SEL4_GLOBAL                    = 0x0,
818 	PERFCOUNTER_STATE_SEL4_LOCAL                     = 0x1,
819 } PERFCOUNTER_STATE_SEL4;
820 typedef enum PERFCOUNTER_CNT5_STATE {
821 	PERFCOUNTER_CNT5_STATE_RESET                     = 0x0,
822 	PERFCOUNTER_CNT5_STATE_START                     = 0x1,
823 	PERFCOUNTER_CNT5_STATE_FREEZE                    = 0x2,
824 	PERFCOUNTER_CNT5_STATE_HW                        = 0x3,
825 } PERFCOUNTER_CNT5_STATE;
826 typedef enum PERFCOUNTER_STATE_SEL5 {
827 	PERFCOUNTER_STATE_SEL5_GLOBAL                    = 0x0,
828 	PERFCOUNTER_STATE_SEL5_LOCAL                     = 0x1,
829 } PERFCOUNTER_STATE_SEL5;
830 typedef enum PERFCOUNTER_CNT6_STATE {
831 	PERFCOUNTER_CNT6_STATE_RESET                     = 0x0,
832 	PERFCOUNTER_CNT6_STATE_START                     = 0x1,
833 	PERFCOUNTER_CNT6_STATE_FREEZE                    = 0x2,
834 	PERFCOUNTER_CNT6_STATE_HW                        = 0x3,
835 } PERFCOUNTER_CNT6_STATE;
836 typedef enum PERFCOUNTER_STATE_SEL6 {
837 	PERFCOUNTER_STATE_SEL6_GLOBAL                    = 0x0,
838 	PERFCOUNTER_STATE_SEL6_LOCAL                     = 0x1,
839 } PERFCOUNTER_STATE_SEL6;
840 typedef enum PERFCOUNTER_CNT7_STATE {
841 	PERFCOUNTER_CNT7_STATE_RESET                     = 0x0,
842 	PERFCOUNTER_CNT7_STATE_START                     = 0x1,
843 	PERFCOUNTER_CNT7_STATE_FREEZE                    = 0x2,
844 	PERFCOUNTER_CNT7_STATE_HW                        = 0x3,
845 } PERFCOUNTER_CNT7_STATE;
846 typedef enum PERFCOUNTER_STATE_SEL7 {
847 	PERFCOUNTER_STATE_SEL7_GLOBAL                    = 0x0,
848 	PERFCOUNTER_STATE_SEL7_LOCAL                     = 0x1,
849 } PERFCOUNTER_STATE_SEL7;
850 typedef enum PERFMON_STATE {
851 	PERFMON_STATE_RESET                              = 0x0,
852 	PERFMON_STATE_START                              = 0x1,
853 	PERFMON_STATE_FREEZE                             = 0x2,
854 	PERFMON_STATE_HW                                 = 0x3,
855 } PERFMON_STATE;
856 typedef enum PERFMON_CNTOFF_AND_OR {
857 	PERFMON_CNTOFF_OR                                = 0x0,
858 	PERFMON_CNTOFF_AND                               = 0x1,
859 } PERFMON_CNTOFF_AND_OR;
860 typedef enum PERFMON_CNTOFF_INT_EN {
861 	PERFMON_CNTOFF_INT_DISABLE                       = 0x0,
862 	PERFMON_CNTOFF_INT_ENABLE                        = 0x1,
863 } PERFMON_CNTOFF_INT_EN;
864 typedef enum PERFMON_CNTOFF_INT_TYPE {
865 	PERFMON_CNTOFF_INT_TYPE_LEVEL                    = 0x0,
866 	PERFMON_CNTOFF_INT_TYPE_PULSE                    = 0x1,
867 } PERFMON_CNTOFF_INT_TYPE;
868 typedef enum ENABLE {
869 	DISABLE_THE_FEATURE                              = 0x0,
870 	ENABLE_THE_FEATURE                               = 0x1,
871 } ENABLE;
872 typedef enum ENABLE_CLOCK {
873 	DISABLE_THE_CLOCK                                = 0x0,
874 	ENABLE_THE_CLOCK                                 = 0x1,
875 } ENABLE_CLOCK;
876 typedef enum FORCE_VBI {
877 	FORCE_VBI_LOW                                    = 0x0,
878 	FORCE_VBI_HIGH                                   = 0x1,
879 } FORCE_VBI;
880 typedef enum OVERRIDE_CGTT_SCLK {
881 	OVERRIDE_CGTT_SCLK_NOOP                          = 0x0,
882 	SET_OVERRIDE_CGTT_SCLK                           = 0x1,
883 } OVERRIDE_CGTT_SCLK;
884 typedef enum CLEAR_SMU_INTR {
885 	SMU_INTR_STATUS_NOOP                             = 0x0,
886 	SMU_INTR_STATUS_CLEAR                            = 0x1,
887 } CLEAR_SMU_INTR;
888 typedef enum STATIC_SCREEN_SMU_INTR {
889 	STATIC_SCREEN_SMU_INTR_NOOP                      = 0x0,
890 	SET_STATIC_SCREEN_SMU_INTR                       = 0x1,
891 } STATIC_SCREEN_SMU_INTR;
892 typedef enum JITTER_REMOVE_DISABLE {
893 	ENABLE_JITTER_REMOVAL                            = 0x0,
894 	DISABLE_JITTER_REMOVAL                           = 0x1,
895 } JITTER_REMOVE_DISABLE;
896 typedef enum DISABLE_CLOCK_GATING {
897 	CLOCK_GATING_ENABLED                             = 0x0,
898 	CLOCK_GATING_DISABLED                            = 0x1,
899 } DISABLE_CLOCK_GATING;
900 typedef enum DISABLE_CLOCK_GATING_IN_DCO {
901 	CLOCK_GATING_ENABLED_IN_DCO                      = 0x0,
902 	CLOCK_GATING_DISABLED_IN_DCO                     = 0x1,
903 } DISABLE_CLOCK_GATING_IN_DCO;
904 typedef enum DCCG_DEEP_COLOR_CNTL {
905 	DCCG_DEEP_COLOR_DTO_DISABLE                      = 0x0,
906 	DCCG_DEEP_COLOR_DTO_5_4_RATIO                    = 0x1,
907 	DCCG_DEEP_COLOR_DTO_3_2_RATIO                    = 0x2,
908 	DCCG_DEEP_COLOR_DTO_2_1_RATIO                    = 0x3,
909 } DCCG_DEEP_COLOR_CNTL;
910 typedef enum REFCLK_CLOCK_EN {
911 	REFCLK_CLOCK_EN_PCIE_REFCLK                      = 0x0,
912 	REFCLK_CLOCK_EN_ALLOW_SRC                        = 0x1,
913 } REFCLK_CLOCK_EN;
914 typedef enum REFCLK_SRC_SEL {
915 	REFCLK_SRC_SEL_XTALIN                            = 0x0,
916 	REFCLK_SRC_SEL_DISPPLL                           = 0x1,
917 } REFCLK_SRC_SEL;
918 typedef enum DPREFCLK_SRC_SEL {
919 	DPREFCLK_SRC_SEL_CK                              = 0x0,
920 	DPREFCLK_SRC_SEL_P0PLL                           = 0x1,
921 	DPREFCLK_SRC_SEL_P1PLL                           = 0x2,
922 	DPREFCLK_SRC_SEL_P2PLL                           = 0x3,
923 	DPREFCLK_SRC_SEL_P3PLL                           = 0x4,
924 } DPREFCLK_SRC_SEL;
925 typedef enum XTAL_REF_SEL {
926 	XTAL_REF_SEL_1X                                  = 0x0,
927 	XTAL_REF_SEL_2X                                  = 0x1,
928 } XTAL_REF_SEL;
929 typedef enum XTAL_REF_CLOCK_SOURCE_SEL {
930 	XTAL_REF_CLOCK_SOURCE_SEL_XTALIN                 = 0x0,
931 	XTAL_REF_CLOCK_SOURCE_SEL_PPLL                   = 0x1,
932 } XTAL_REF_CLOCK_SOURCE_SEL;
933 typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL {
934 	MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN            = 0x0,
935 	MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK       = 0x1,
936 } MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL;
937 typedef enum ALLOW_SR_ON_TRANS_REQ {
938 	ALLOW_SR_ON_TRANS_REQ_ENABLE                     = 0x0,
939 	ALLOW_SR_ON_TRANS_REQ_DISABLE                    = 0x1,
940 } ALLOW_SR_ON_TRANS_REQ;
941 typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL {
942 	MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN            = 0x0,
943 	MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK       = 0x1,
944 } MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL;
945 typedef enum PIPE_PIXEL_RATE_SOURCE {
946 	PIPE_PIXEL_RATE_SOURCE_P0PLL                     = 0x0,
947 	PIPE_PIXEL_RATE_SOURCE_P1PLL                     = 0x1,
948 	PIPE_PIXEL_RATE_SOURCE_P2PLL                     = 0x2,
949 } PIPE_PIXEL_RATE_SOURCE;
950 typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE {
951 	PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA            = 0x0,
952 	PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB            = 0x1,
953 	PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC            = 0x2,
954 	PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD            = 0x3,
955 	PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE            = 0x4,
956 	PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF            = 0x5,
957 	PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG            = 0x6,
958 } PIPE_PHYPLL_PIXEL_RATE_SOURCE;
959 typedef enum PIPE_PIXEL_RATE_PLL_SOURCE {
960 	PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL                = 0x0,
961 	PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL               = 0x1,
962 } PIPE_PIXEL_RATE_PLL_SOURCE;
963 typedef enum DP_DTO_DS_DISABLE {
964 	DP_DTO_DESPREAD_DISABLE                          = 0x0,
965 	DP_DTO_DESPREAD_ENABLE                           = 0x1,
966 } DP_DTO_DS_DISABLE;
967 typedef enum CRTC_ADD_PIXEL {
968 	CRTC_ADD_PIXEL_NOOP                              = 0x0,
969 	CRTC_ADD_PIXEL_FORCE                             = 0x1,
970 } CRTC_ADD_PIXEL;
971 typedef enum CRTC_DROP_PIXEL {
972 	CRTC_DROP_PIXEL_NOOP                             = 0x0,
973 	CRTC_DROP_PIXEL_FORCE                            = 0x1,
974 } CRTC_DROP_PIXEL;
975 typedef enum SYMCLK_FE_FORCE_EN {
976 	SYMCLK_FE_FORCE_EN_DISABLE                       = 0x0,
977 	SYMCLK_FE_FORCE_EN_ENABLE                        = 0x1,
978 } SYMCLK_FE_FORCE_EN;
979 typedef enum SYMCLK_FE_FORCE_SRC {
980 	SYMCLK_FE_FORCE_SRC_UNIPHYA                      = 0x0,
981 	SYMCLK_FE_FORCE_SRC_UNIPHYB                      = 0x1,
982 	SYMCLK_FE_FORCE_SRC_UNIPHYC                      = 0x2,
983 	SYMCLK_FE_FORCE_SRC_UNIPHYD                      = 0x3,
984 	SYMCLK_FE_FORCE_SRC_UNIPHYE                      = 0x4,
985 	SYMCLK_FE_FORCE_SRC_UNIPHYF                      = 0x5,
986 	SYMCLK_FE_FORCE_SRC_UNIPHYG                      = 0x6,
987 } SYMCLK_FE_FORCE_SRC;
988 typedef enum DPDBG_CLK_FORCE_EN {
989 	DPDBG_CLK_FORCE_EN_DISABLE                       = 0x0,
990 	DPDBG_CLK_FORCE_EN_ENABLE                        = 0x1,
991 } DPDBG_CLK_FORCE_EN;
992 typedef enum DVOACLK_COARSE_SKEW_CNTL {
993 	DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT           = 0x0,
994 	DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP            = 0x1,
995 	DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS           = 0x2,
996 	DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS           = 0x3,
997 	DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS           = 0x4,
998 	DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS           = 0x5,
999 	DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS           = 0x6,
1000 	DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS           = 0x7,
1001 	DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS           = 0x8,
1002 	DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS           = 0x9,
1003 	DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS          = 0xa,
1004 	DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS          = 0xb,
1005 	DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS          = 0xc,
1006 	DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS          = 0xd,
1007 	DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS          = 0xe,
1008 	DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS          = 0xf,
1009 	DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP            = 0x10,
1010 	DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS           = 0x11,
1011 	DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS           = 0x12,
1012 	DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS           = 0x13,
1013 	DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS           = 0x14,
1014 	DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS           = 0x15,
1015 	DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS           = 0x16,
1016 	DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS           = 0x17,
1017 	DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS           = 0x18,
1018 	DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS          = 0x19,
1019 	DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS          = 0x1a,
1020 	DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS          = 0x1b,
1021 	DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS          = 0x1c,
1022 	DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS          = 0x1d,
1023 	DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS          = 0x1e,
1024 } DVOACLK_COARSE_SKEW_CNTL;
1025 typedef enum DVOACLK_FINE_SKEW_CNTL {
1026 	DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT             = 0x0,
1027 	DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP              = 0x1,
1028 	DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS             = 0x2,
1029 	DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS             = 0x3,
1030 	DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP              = 0x4,
1031 	DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS             = 0x5,
1032 	DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS             = 0x6,
1033 	DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS             = 0x7,
1034 } DVOACLK_FINE_SKEW_CNTL;
1035 typedef enum DVOACLKD_IN_PHASE {
1036 	DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO         = 0x0,
1037 	DVOACLKD_IN_PHASE_WITH_PCLK_DVO                  = 0x1,
1038 } DVOACLKD_IN_PHASE;
1039 typedef enum DVOACLKC_IN_PHASE {
1040 	DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO         = 0x0,
1041 	DVOACLKC_IN_PHASE_WITH_PCLK_DVO                  = 0x1,
1042 } DVOACLKC_IN_PHASE;
1043 typedef enum DVOACLKC_MVP_IN_PHASE {
1044 	DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO     = 0x0,
1045 	DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO              = 0x1,
1046 } DVOACLKC_MVP_IN_PHASE;
1047 typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE {
1048 	DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE         = 0x0,
1049 	DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE          = 0x1,
1050 } DVOACLKC_MVP_SKEW_PHASE_OVERRIDE;
1051 typedef enum MVP_CLK_SRC_SEL {
1052 	MVP_CLK_SRC_SEL_RSRV                             = 0x0,
1053 	MVP_CLK_SRC_SEL_IO_1                             = 0x1,
1054 	MVP_CLK_SRC_SEL_IO_2                             = 0x2,
1055 	MVP_CLK_SRC_SEL_REFCLK                           = 0x3,
1056 } MVP_CLK_SRC_SEL;
1057 typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL {
1058 	DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0                 = 0x0,
1059 	DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1                 = 0x1,
1060 	DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2                 = 0x2,
1061 	DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3                 = 0x3,
1062 	DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4                 = 0x4,
1063 	DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5                 = 0x5,
1064 	DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED              = 0x6,
1065 } DCCG_AUDIO_DTO0_SOURCE_SEL;
1066 typedef enum DCCG_AUDIO_DTO_SEL {
1067 	DCCG_AUDIO_DTO_SEL_AUDIO_DTO0                    = 0x0,
1068 	DCCG_AUDIO_DTO_SEL_AUDIO_DTO1                    = 0x1,
1069 	DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO                  = 0x2,
1070 } DCCG_AUDIO_DTO_SEL;
1071 typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL {
1072 	DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0                = 0x0,
1073 	DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1                = 0x1,
1074 } DCCG_AUDIO_DTO2_SOURCE_SEL;
1075 typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO {
1076 	DCCG_AUDIO_DTO_USE_128FBR_FOR_DP                 = 0x0,
1077 	DCCG_AUDIO_DTO_USE_512FBR_FOR_DP                 = 0x1,
1078 } DCCG_AUDIO_DTO_USE_512FBR_DTO;
1079 typedef enum DCCG_DBG_EN {
1080 	DCCG_DBG_EN_DISABLE                              = 0x0,
1081 	DCCG_DBG_EN_ENABLE                               = 0x1,
1082 } DCCG_DBG_EN;
1083 typedef enum DCCG_DBG_BLOCK_SEL {
1084 	DCCG_DBG_BLOCK_SEL_DCCG                          = 0x0,
1085 	DCCG_DBG_BLOCK_SEL_PMON                          = 0x1,
1086 	DCCG_DBG_BLOCK_SEL_PMON2                         = 0x2,
1087 } DCCG_DBG_BLOCK_SEL;
1088 typedef enum DCCG_DBG_CLOCK_SEL {
1089 	DCCG_DBG_CLOCK_SEL_DISPCLK                       = 0x0,
1090 	DCCG_DBG_CLOCK_SEL_SCLK                          = 0x1,
1091 	DCCG_DBG_CLOCK_SEL_MVPCLK                        = 0x2,
1092 	DCCG_DBG_CLOCK_SEL_DVOCLK                        = 0x3,
1093 	DCCG_DBG_CLOCK_SEL_DACCLK                        = 0x4,
1094 	DCCG_DBG_CLOCK_SEL_REFCLK                        = 0x5,
1095 	DCCG_DBG_CLOCK_SEL_SYMCLKA                       = 0x6,
1096 	DCCG_DBG_CLOCK_SEL_SYMCLKB                       = 0x7,
1097 	DCCG_DBG_CLOCK_SEL_SYMCLKC                       = 0x8,
1098 	DCCG_DBG_CLOCK_SEL_SYMCLKD                       = 0x9,
1099 	DCCG_DBG_CLOCK_SEL_SYMCLKE                       = 0xa,
1100 	DCCG_DBG_CLOCK_SEL_SYMCLKG                       = 0xb,
1101 	DCCG_DBG_CLOCK_SEL_SYMCLKF                       = 0xc,
1102 	DCCG_DBG_CLOCK_SEL_RSRV                          = 0xd,
1103 	DCCG_DBG_CLOCK_SEL_AOMCLK0                       = 0xe,
1104 	DCCG_DBG_CLOCK_SEL_AOMCLK1                       = 0xf,
1105 	DCCG_DBG_CLOCK_SEL_AOMCLK2                       = 0x10,
1106 	DCCG_DBG_CLOCK_SEL_DPREFCLK                      = 0x11,
1107 	DCCG_DBG_CLOCK_SEL_UNB_DB_CLK                    = 0x12,
1108 	DCCG_DBG_CLOCK_SEL_DSICLK                        = 0x13,
1109 	DCCG_DBG_CLOCK_SEL_BYTECLK                       = 0x14,
1110 	DCCG_DBG_CLOCK_SEL_ESCCLK                        = 0x15,
1111 	DCCG_DBG_CLOCK_SEL_SYMCLKLPA                     = 0x16,
1112 	DCCG_DBG_CLOCK_SEL_SYMCLKLPB                     = 0x17,
1113 } DCCG_DBG_CLOCK_SEL;
1114 typedef enum DCCG_DBG_OUT_BLOCK_SEL {
1115 	DCCG_DBG_OUT_BLOCK_SEL_DCCG                      = 0x0,
1116 	DCCG_DBG_OUT_BLOCK_SEL_DCO                       = 0x1,
1117 	DCCG_DBG_OUT_BLOCK_SEL_DCIO                      = 0x2,
1118 	DCCG_DBG_OUT_BLOCK_SEL_DSI                       = 0x3,
1119 } DCCG_DBG_OUT_BLOCK_SEL;
1120 typedef enum DISPCLK_FREQ_RAMP_DONE {
1121 	DISPCLK_FREQ_RAMP_IN_PROGRESS                    = 0x0,
1122 	DISPCLK_FREQ_RAMP_COMPLETED                      = 0x1,
1123 } DISPCLK_FREQ_RAMP_DONE;
1124 typedef enum DCCG_FIFO_ERRDET_RESET {
1125 	DCCG_FIFO_ERRDET_RESET_NOOP                      = 0x0,
1126 	DCCG_FIFO_ERRDET_RESET_FORCE                     = 0x1,
1127 } DCCG_FIFO_ERRDET_RESET;
1128 typedef enum DCCG_FIFO_ERRDET_STATE {
1129 	DCCG_FIFO_ERRDET_STATE_DETECTION                 = 0x0,
1130 	DCCG_FIFO_ERRDET_STATE_CALIBRATION               = 0x1,
1131 } DCCG_FIFO_ERRDET_STATE;
1132 typedef enum DCCG_FIFO_ERRDET_OVR_EN {
1133 	DCCG_FIFO_ERRDET_OVR_DISABLE                     = 0x0,
1134 	DCCG_FIFO_ERRDET_OVR_ENABLE                      = 0x1,
1135 } DCCG_FIFO_ERRDET_OVR_EN;
1136 typedef enum DISPCLK_CHG_FWD_CORR_DISABLE {
1137 	DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING         = 0x0,
1138 	DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING        = 0x1,
1139 } DISPCLK_CHG_FWD_CORR_DISABLE;
1140 typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS {
1141 	DC_MEM_GLOBAL_PWR_REQ_ENABLE                     = 0x0,
1142 	DC_MEM_GLOBAL_PWR_REQ_DISABLE                    = 0x1,
1143 } DC_MEM_GLOBAL_PWR_REQ_DIS;
1144 typedef enum DCCG_PERF_RUN {
1145 	DCCG_PERF_RUN_NOOP                               = 0x0,
1146 	DCCG_PERF_RUN_START                              = 0x1,
1147 } DCCG_PERF_RUN;
1148 typedef enum DCCG_PERF_MODE_VSYNC {
1149 	DCCG_PERF_MODE_VSYNC_NOOP                        = 0x0,
1150 	DCCG_PERF_MODE_VSYNC_START                       = 0x1,
1151 } DCCG_PERF_MODE_VSYNC;
1152 typedef enum DCCG_PERF_MODE_HSYNC {
1153 	DCCG_PERF_MODE_HSYNC_NOOP                        = 0x0,
1154 	DCCG_PERF_MODE_HSYNC_START                       = 0x1,
1155 } DCCG_PERF_MODE_HSYNC;
1156 typedef enum DCCG_PERF_CRTC_SELECT {
1157 	DCCG_PERF_SEL_CRTC0                              = 0x0,
1158 	DCCG_PERF_SEL_CRTC1                              = 0x1,
1159 	DCCG_PERF_SEL_CRTC2                              = 0x2,
1160 	DCCG_PERF_SEL_CRTC3                              = 0x3,
1161 	DCCG_PERF_SEL_CRTC4                              = 0x4,
1162 	DCCG_PERF_SEL_CRTC5                              = 0x5,
1163 } DCCG_PERF_CRTC_SELECT;
1164 typedef enum CLOCK_BRANCH_SOFT_RESET {
1165 	CLOCK_BRANCH_SOFT_RESET_NOOP                     = 0x0,
1166 	CLOCK_BRANCH_SOFT_RESET_FORCE                    = 0x1,
1167 } CLOCK_BRANCH_SOFT_RESET;
1168 typedef enum PLL_CFG_IF_SOFT_RESET {
1169 	PLL_CFG_IF_SOFT_RESET_NOOP                       = 0x0,
1170 	PLL_CFG_IF_SOFT_RESET_FORCE                      = 0x1,
1171 } PLL_CFG_IF_SOFT_RESET;
1172 typedef enum DVO_ENABLE_RST {
1173 	DVO_ENABLE_RST_DISABLE                           = 0x0,
1174 	DVO_ENABLE_RST_ENABLE                            = 0x1,
1175 } DVO_ENABLE_RST;
1176 typedef enum LptNumBanks {
1177 	LPT_NUM_BANKS_2BANK                              = 0x0,
1178 	LPT_NUM_BANKS_4BANK                              = 0x1,
1179 	LPT_NUM_BANKS_8BANK                              = 0x2,
1180 	LPT_NUM_BANKS_16BANK                             = 0x3,
1181 	LPT_NUM_BANKS_32BANK                             = 0x4,
1182 } LptNumBanks;
1183 typedef enum DCIO_DC_GENERICA_SEL {
1184 	DCIO_GENERICA_SEL_DACA_STEREOSYNC                = 0x0,
1185 	DCIO_GENERICA_SEL_STEREOSYNC                     = 0x1,
1186 	DCIO_GENERICA_SEL_DACA_PIXCLK                    = 0x2,
1187 	DCIO_GENERICA_SEL_DACB_PIXCLK                    = 0x3,
1188 	DCIO_GENERICA_SEL_DVOA_CTL3                      = 0x4,
1189 	DCIO_GENERICA_SEL_P1_PLLCLK                      = 0x5,
1190 	DCIO_GENERICA_SEL_P2_PLLCLK                      = 0x6,
1191 	DCIO_GENERICA_SEL_DVOA_STEREOSYNC                = 0x7,
1192 	DCIO_GENERICA_SEL_DACA_FIELD_NUMBER              = 0x8,
1193 	DCIO_GENERICA_SEL_DACB_FIELD_NUMBER              = 0x9,
1194 	DCIO_GENERICA_SEL_GENERICA_DCCG                  = 0xa,
1195 	DCIO_GENERICA_SEL_SYNCEN                         = 0xb,
1196 	DCIO_GENERICA_SEL_GENERICA_SCG                   = 0xc,
1197 	DCIO_GENERICA_SEL_RESERVED_VALUE13               = 0xd,
1198 	DCIO_GENERICA_SEL_RESERVED_VALUE14               = 0xe,
1199 	DCIO_GENERICA_SEL_RESERVED_VALUE15               = 0xf,
1200 	DCIO_GENERICA_SEL_GENERICA_DPRX                  = 0x10,
1201 	DCIO_GENERICA_SEL_GENERICB_DPRX                  = 0x11,
1202 } DCIO_DC_GENERICA_SEL;
1203 typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
1204 	DCIO_UNIPHYA_TEST_REFDIV_CLK                     = 0x0,
1205 	DCIO_UNIPHYB_TEST_REFDIV_CLK                     = 0x1,
1206 	DCIO_UNIPHYC_TEST_REFDIV_CLK                     = 0x2,
1207 	DCIO_UNIPHYD_TEST_REFDIV_CLK                     = 0x3,
1208 	DCIO_UNIPHYE_TEST_REFDIV_CLK                     = 0x4,
1209 	DCIO_UNIPHYF_TEST_REFDIV_CLK                     = 0x5,
1210 	DCIO_UNIPHYG_TEST_REFDIV_CLK                     = 0x6,
1211 	DCIO_UNIPHYLPA_TEST_REFDIV_CLK                   = 0x7,
1212 	DCIO_UNIPHYLPB_TEST_REFDIV_CLK                   = 0x8,
1213 } DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
1214 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
1215 	DCIO_UNIPHYA_FBDIV_CLK                           = 0x0,
1216 	DCIO_UNIPHYB_FBDIV_CLK                           = 0x1,
1217 	DCIO_UNIPHYC_FBDIV_CLK                           = 0x2,
1218 	DCIO_UNIPHYD_FBDIV_CLK                           = 0x3,
1219 	DCIO_UNIPHYE_FBDIV_CLK                           = 0x4,
1220 	DCIO_UNIPHYF_FBDIV_CLK                           = 0x5,
1221 	DCIO_UNIPHYG_FBDIV_CLK                           = 0x6,
1222 	DCIO_UNIPHYLPA_FBDIV_CLK                         = 0x7,
1223 	DCIO_UNIPHYLPB_FBDIV_CLK                         = 0x8,
1224 } DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
1225 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
1226 	DCIO_UNIPHYA_FBDIV_SSC_CLK                       = 0x0,
1227 	DCIO_UNIPHYB_FBDIV_SSC_CLK                       = 0x1,
1228 	DCIO_UNIPHYC_FBDIV_SSC_CLK                       = 0x2,
1229 	DCIO_UNIPHYD_FBDIV_SSC_CLK                       = 0x3,
1230 	DCIO_UNIPHYE_FBDIV_SSC_CLK                       = 0x4,
1231 	DCIO_UNIPHYF_FBDIV_SSC_CLK                       = 0x5,
1232 	DCIO_UNIPHYG_FBDIV_SSC_CLK                       = 0x6,
1233 	DCIO_UNIPHYLPA_FBDIV_SSC_CLK                     = 0x7,
1234 	DCIO_UNIPHYLPB_FBDIV_SSC_CLK                     = 0x8,
1235 } DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
1236 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
1237 	DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2                 = 0x0,
1238 	DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2                 = 0x1,
1239 	DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2                 = 0x2,
1240 	DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2                 = 0x3,
1241 	DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2                 = 0x4,
1242 	DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2                 = 0x5,
1243 	DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2                 = 0x6,
1244 	DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2               = 0x7,
1245 	DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2               = 0x8,
1246 } DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
1247 typedef enum DCIO_DC_GENERICB_SEL {
1248 	DCIO_GENERICB_SEL_DACA_STEREOSYNC                = 0x0,
1249 	DCIO_GENERICB_SEL_STEREOSYNC                     = 0x1,
1250 	DCIO_GENERICB_SEL_DACA_PIXCLK                    = 0x2,
1251 	DCIO_GENERICB_SEL_DACB_PIXCLK                    = 0x3,
1252 	DCIO_GENERICB_SEL_DVOA_CTL3                      = 0x4,
1253 	DCIO_GENERICB_SEL_P1_PLLCLK                      = 0x5,
1254 	DCIO_GENERICB_SEL_P2_PLLCLK                      = 0x6,
1255 	DCIO_GENERICB_SEL_DVOA_STEREOSYNC                = 0x7,
1256 	DCIO_GENERICB_SEL_DACA_FIELD_NUMBER              = 0x8,
1257 	DCIO_GENERICB_SEL_DACB_FIELD_NUMBER              = 0x9,
1258 	DCIO_GENERICB_SEL_GENERICB_DCCG                  = 0xa,
1259 	DCIO_GENERICB_SEL_SYNCEN                         = 0xb,
1260 	DCIO_GENERICB_SEL_GENERICA_SCG                   = 0xc,
1261 	DCIO_GENERICB_SEL_RESERVED_VALUE13               = 0xd,
1262 	DCIO_GENERICB_SEL_RESERVED_VALUE14               = 0xe,
1263 	DCIO_GENERICB_SEL_RESERVED_VALUE15               = 0xf,
1264 } DCIO_DC_GENERICB_SEL;
1265 typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL {
1266 	DCIO_DC_PAD_EXTERN_SIG_SEL_MVP                   = 0x0,
1267 	DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA                = 0x1,
1268 	DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK             = 0x2,
1269 	DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC           = 0x3,
1270 	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA              = 0x4,
1271 	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB              = 0x5,
1272 	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC              = 0x6,
1273 	DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1                  = 0x7,
1274 	DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2                  = 0x8,
1275 	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK               = 0x9,
1276 	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA              = 0xa,
1277 	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK               = 0xb,
1278 	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA              = 0xc,
1279 	DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1                 = 0xd,
1280 	DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0                 = 0xe,
1281 	DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL                = 0xf,
1282 } DCIO_DC_PAD_EXTERN_SIG_SEL;
1283 typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS {
1284 	DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA                 = 0x0,
1285 	DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE       = 0x1,
1286 	DCIO_MVP_PIXEL_SRC_STATUS_CRTC                   = 0x2,
1287 	DCIO_MVP_PIXEL_SRC_STATUS_LB                     = 0x3,
1288 } DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS;
1289 typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
1290 	DCIO_HSYNCA_OUTPUT_SEL_DISABLE                   = 0x0,
1291 	DCIO_HSYNCA_OUTPUT_SEL_PPLL1                     = 0x1,
1292 	DCIO_HSYNCA_OUTPUT_SEL_PPLL2                     = 0x2,
1293 	DCIO_HSYNCA_OUTPUT_SEL_RESERVED                  = 0x3,
1294 } DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;
1295 typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
1296 	DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE                = 0x0,
1297 	DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1                  = 0x1,
1298 	DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2                  = 0x2,
1299 	DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3        = 0x3,
1300 } DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
1301 typedef enum DCIO_DC_GPIO_VIP_DEBUG {
1302 	DCIO_DC_GPIO_VIP_DEBUG_NORMAL                    = 0x0,
1303 	DCIO_DC_GPIO_VIP_DEBUG_CG_BIG                    = 0x1,
1304 } DCIO_DC_GPIO_VIP_DEBUG;
1305 typedef enum DCIO_DC_GPIO_MACRO_DEBUG {
1306 	DCIO_DC_GPIO_MACRO_DEBUG_NORMAL                  = 0x0,
1307 	DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF                = 0x1,
1308 	DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2         = 0x2,
1309 	DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3         = 0x3,
1310 } DCIO_DC_GPIO_MACRO_DEBUG;
1311 typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL {
1312 	DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL       = 0x0,
1313 	DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP         = 0x1,
1314 } DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL;
1315 typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN {
1316 	DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS            = 0x0,
1317 	DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE            = 0x1,
1318 } DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN;
1319 typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
1320 	DCIO_DPRX_LOOPBACK_ENABLE_NORMAL                 = 0x0,
1321 	DCIO_DPRX_LOOPBACK_ENABLE_LOOP                   = 0x1,
1322 } DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE;
1323 typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
1324 	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x0,
1325 	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x1,
1326 	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS= 0x2,
1327 	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS= 0x3,
1328 	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS= 0x4,
1329 	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS= 0x5,
1330 	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS= 0x6,
1331 	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS= 0x7,
1332 } DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION;
1333 typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
1334 	DCIO_UNIPHY_CHANNEL_NO_INVERSION                 = 0x0,
1335 	DCIO_UNIPHY_CHANNEL_INVERTED                     = 0x1,
1336 } DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
1337 typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
1338 	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW        = 0x0,
1339 	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW           = 0x1,
1340 	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x2,
1341 	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED= 0x3,
1342 } DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
1343 typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
1344 	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0              = 0x0,
1345 	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1              = 0x1,
1346 	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2              = 0x2,
1347 	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3              = 0x3,
1348 } DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
1349 typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
1350 	DCIO_VIP_MUX_EN_DVO                              = 0x0,
1351 	DCIO_VIP_MUX_EN_VIP                              = 0x1,
1352 } DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN;
1353 typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
1354 	DCIO_VIP_ALTER_MAPPING_EN_DEFAULT                = 0x0,
1355 	DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE            = 0x1,
1356 } DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN;
1357 typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
1358 	DCIO_DVO_ALTER_MAPPING_EN_DEFAULT                = 0x0,
1359 	DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE            = 0x1,
1360 } DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN;
1361 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
1362 	DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE= 0x0,
1363 	DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE= 0x1,
1364 } DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN;
1365 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
1366 	DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF           = 0x0,
1367 	DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON            = 0x1,
1368 } DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE;
1369 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
1370 	DCIO_LVTMA_SYNCEN_POL_NON_INVERT                 = 0x0,
1371 	DCIO_LVTMA_SYNCEN_POL_INVERT                     = 0x1,
1372 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL;
1373 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
1374 	DCIO_LVTMA_DIGON_OFF                             = 0x0,
1375 	DCIO_LVTMA_DIGON_ON                              = 0x1,
1376 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON;
1377 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
1378 	DCIO_LVTMA_DIGON_POL_NON_INVERT                  = 0x0,
1379 	DCIO_LVTMA_DIGON_POL_INVERT                      = 0x1,
1380 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL;
1381 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
1382 	DCIO_LVTMA_BLON_OFF                              = 0x0,
1383 	DCIO_LVTMA_BLON_ON                               = 0x1,
1384 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON;
1385 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
1386 	DCIO_LVTMA_BLON_POL_NON_INVERT                   = 0x0,
1387 	DCIO_LVTMA_BLON_POL_INVERT                       = 0x1,
1388 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL;
1389 typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
1390 	DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON              = 0x0,
1391 	DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE          = 0x1,
1392 } DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN;
1393 typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
1394 	DCIO_BL_PWM_FRACTIONAL_DISABLE                   = 0x0,
1395 	DCIO_BL_PWM_FRACTIONAL_ENABLE                    = 0x1,
1396 } DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
1397 typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
1398 	DCIO_BL_PWM_DISABLE                              = 0x0,
1399 	DCIO_BL_PWM_ENABLE                               = 0x1,
1400 } DCIO_BL_PWM_CNTL_BL_PWM_EN;
1401 typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
1402 	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL       = 0x0,
1403 	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1       = 0x1,
1404 	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2       = 0x2,
1405 	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3       = 0x3,
1406 } DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT;
1407 typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
1408 	DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE              = 0x0,
1409 	DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE               = 0x1,
1410 } DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
1411 typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
1412 	DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL      = 0x0,
1413 	DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM         = 0x1,
1414 } DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN;
1415 typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
1416 	DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE                = 0x0,
1417 	DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE                 = 0x1,
1418 } DCIO_BL_PWM_GRP1_REG_LOCK;
1419 typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
1420 	DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE   = 0x0,
1421 	DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE    = 0x1,
1422 } DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
1423 typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
1424 	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1= 0x0,
1425 	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2= 0x1,
1426 	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3= 0x2,
1427 	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4= 0x3,
1428 	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5= 0x4,
1429 	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6= 0x5,
1430 } DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
1431 typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
1432 	DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x0,
1433 	DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM= 0x1,
1434 } DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
1435 typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
1436 	DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE       = 0x0,
1437 	DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE      = 0x1,
1438 } DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
1439 typedef enum DCIO_GSL_SEL {
1440 	DCIO_GSL_SEL_GROUP_0                             = 0x0,
1441 	DCIO_GSL_SEL_GROUP_1                             = 0x1,
1442 	DCIO_GSL_SEL_GROUP_2                             = 0x2,
1443 } DCIO_GSL_SEL;
1444 typedef enum DCIO_GENLK_CLK_GSL_MASK {
1445 	DCIO_GENLK_CLK_GSL_MASK_NO                       = 0x0,
1446 	DCIO_GENLK_CLK_GSL_MASK_TIMING                   = 0x1,
1447 	DCIO_GENLK_CLK_GSL_MASK_STEREO                   = 0x2,
1448 } DCIO_GENLK_CLK_GSL_MASK;
1449 typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
1450 	DCIO_GENLK_VSYNC_GSL_MASK_NO                     = 0x0,
1451 	DCIO_GENLK_VSYNC_GSL_MASK_TIMING                 = 0x1,
1452 	DCIO_GENLK_VSYNC_GSL_MASK_STEREO                 = 0x2,
1453 } DCIO_GENLK_VSYNC_GSL_MASK;
1454 typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
1455 	DCIO_SWAPLOCK_A_GSL_MASK_NO                      = 0x0,
1456 	DCIO_SWAPLOCK_A_GSL_MASK_TIMING                  = 0x1,
1457 	DCIO_SWAPLOCK_A_GSL_MASK_STEREO                  = 0x2,
1458 } DCIO_SWAPLOCK_A_GSL_MASK;
1459 typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
1460 	DCIO_SWAPLOCK_B_GSL_MASK_NO                      = 0x0,
1461 	DCIO_SWAPLOCK_B_GSL_MASK_TIMING                  = 0x1,
1462 	DCIO_SWAPLOCK_B_GSL_MASK_STEREO                  = 0x2,
1463 } DCIO_SWAPLOCK_B_GSL_MASK;
1464 typedef enum DCIO_GSL_VSYNC_SEL {
1465 	DCIO_GSL_VSYNC_SEL_PIPE0                         = 0x0,
1466 	DCIO_GSL_VSYNC_SEL_PIPE1                         = 0x1,
1467 	DCIO_GSL_VSYNC_SEL_PIPE2                         = 0x2,
1468 	DCIO_GSL_VSYNC_SEL_PIPE3                         = 0x3,
1469 	DCIO_GSL_VSYNC_SEL_PIPE4                         = 0x4,
1470 	DCIO_GSL_VSYNC_SEL_PIPE5                         = 0x5,
1471 } DCIO_GSL_VSYNC_SEL;
1472 typedef enum DCIO_GSL0_TIMING_SYNC_SEL {
1473 	DCIO_GSL0_TIMING_SYNC_SEL_PIPE                   = 0x0,
1474 	DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC           = 0x1,
1475 	DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK             = 0x2,
1476 	DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A             = 0x3,
1477 	DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B             = 0x4,
1478 } DCIO_GSL0_TIMING_SYNC_SEL;
1479 typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL {
1480 	DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION            = 0x0,
1481 	DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC         = 0x1,
1482 	DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK            = 0x2,
1483 	DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A           = 0x3,
1484 	DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B           = 0x4,
1485 } DCIO_GSL0_GLOBAL_UNLOCK_SEL;
1486 typedef enum DCIO_GSL1_TIMING_SYNC_SEL {
1487 	DCIO_GSL1_TIMING_SYNC_SEL_PIPE                   = 0x0,
1488 	DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC           = 0x1,
1489 	DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK             = 0x2,
1490 	DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A             = 0x3,
1491 	DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B             = 0x4,
1492 } DCIO_GSL1_TIMING_SYNC_SEL;
1493 typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL {
1494 	DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION            = 0x0,
1495 	DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC         = 0x1,
1496 	DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK            = 0x2,
1497 	DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A           = 0x3,
1498 	DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B           = 0x4,
1499 } DCIO_GSL1_GLOBAL_UNLOCK_SEL;
1500 typedef enum DCIO_GSL2_TIMING_SYNC_SEL {
1501 	DCIO_GSL2_TIMING_SYNC_SEL_PIPE                   = 0x0,
1502 	DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC           = 0x1,
1503 	DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK             = 0x2,
1504 	DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A             = 0x3,
1505 	DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B             = 0x4,
1506 } DCIO_GSL2_TIMING_SYNC_SEL;
1507 typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL {
1508 	DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION            = 0x0,
1509 	DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC         = 0x1,
1510 	DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK            = 0x2,
1511 	DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A           = 0x3,
1512 	DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B           = 0x4,
1513 } DCIO_GSL2_GLOBAL_UNLOCK_SEL;
1514 typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
1515 	DCIO_GPU_TIMER_START_0_END_27                    = 0x0,
1516 	DCIO_GPU_TIMER_START_1_END_28                    = 0x1,
1517 	DCIO_GPU_TIMER_START_2_END_29                    = 0x2,
1518 	DCIO_GPU_TIMER_START_3_END_30                    = 0x3,
1519 	DCIO_GPU_TIMER_START_4_END_31                    = 0x4,
1520 	DCIO_GPU_TIMER_START_6_END_33                    = 0x5,
1521 	DCIO_GPU_TIMER_START_8_END_35                    = 0x6,
1522 	DCIO_GPU_TIMER_START_10_END_37                   = 0x7,
1523 } DCIO_DC_GPU_TIMER_START_POSITION;
1524 typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
1525 	DCIO_TEST_CLK_SEL_DISPCLK                        = 0x0,
1526 	DCIO_TEST_CLK_SEL_GATED_DISPCLK                  = 0x1,
1527 	DCIO_TEST_CLK_SEL_SCLK                           = 0x2,
1528 } DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
1529 typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
1530 	DCIO_DISPCLK_R_DCIO_GATE_DISABLE                 = 0x0,
1531 	DCIO_DISPCLK_R_DCIO_GATE_ENABLE                  = 0x1,
1532 } DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
1533 typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX {
1534 	DCIO_EXT_VSYNC_MUX_SWAPLOCKB                     = 0x0,
1535 	DCIO_EXT_VSYNC_MUX_CRTC0                         = 0x1,
1536 	DCIO_EXT_VSYNC_MUX_CRTC1                         = 0x2,
1537 	DCIO_EXT_VSYNC_MUX_CRTC2                         = 0x3,
1538 	DCIO_EXT_VSYNC_MUX_CRTC3                         = 0x4,
1539 	DCIO_EXT_VSYNC_MUX_CRTC4                         = 0x5,
1540 	DCIO_EXT_VSYNC_MUX_CRTC5                         = 0x6,
1541 	DCIO_EXT_VSYNC_MUX_GENERICB                      = 0x7,
1542 } DCIO_DCO_DCFE_EXT_VSYNC_MUX;
1543 typedef enum DCIO_DCO_EXT_VSYNC_MASK {
1544 	DCIO_EXT_VSYNC_MASK_NONE                         = 0x0,
1545 	DCIO_EXT_VSYNC_MASK_PIPE0                        = 0x1,
1546 	DCIO_EXT_VSYNC_MASK_PIPE1                        = 0x2,
1547 	DCIO_EXT_VSYNC_MASK_PIPE2                        = 0x3,
1548 	DCIO_EXT_VSYNC_MASK_PIPE3                        = 0x4,
1549 	DCIO_EXT_VSYNC_MASK_PIPE4                        = 0x5,
1550 	DCIO_EXT_VSYNC_MASK_PIPE5                        = 0x6,
1551 	DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE               = 0x7,
1552 } DCIO_DCO_EXT_VSYNC_MASK;
1553 typedef enum DCIO_DBG_OUT_PIN_SEL {
1554 	DCIO_DBG_OUT_PIN_SEL_LOW_12BIT                   = 0x0,
1555 	DCIO_DBG_OUT_PIN_SEL_HIGH_12BIT                  = 0x1,
1556 } DCIO_DBG_OUT_PIN_SEL;
1557 typedef enum DCIO_DBG_OUT_12BIT_SEL {
1558 	DCIO_DBG_OUT_12BIT_SEL_LOW_12BIT                 = 0x0,
1559 	DCIO_DBG_OUT_12BIT_SEL_MID_12BIT                 = 0x1,
1560 	DCIO_DBG_OUT_12BIT_SEL_HIGH_12BIT                = 0x2,
1561 	DCIO_DBG_OUT_12BIT_SEL_OVERRIDE                  = 0x3,
1562 } DCIO_DBG_OUT_12BIT_SEL;
1563 typedef enum DCIO_DSYNC_SOFT_RESET {
1564 	DCIO_DSYNC_SOFT_RESET_DEASSERT                   = 0x0,
1565 	DCIO_DSYNC_SOFT_RESET_ASSERT                     = 0x1,
1566 } DCIO_DSYNC_SOFT_RESET;
1567 typedef enum DCIO_DACA_SOFT_RESET {
1568 	DCIO_DACA_SOFT_RESET_DEASSERT                    = 0x0,
1569 	DCIO_DACA_SOFT_RESET_ASSERT                      = 0x1,
1570 } DCIO_DACA_SOFT_RESET;
1571 typedef enum DCIO_DCRXPHY_SOFT_RESET {
1572 	DCIO_DCRXPHY_SOFT_RESET_DEASSERT                 = 0x0,
1573 	DCIO_DCRXPHY_SOFT_RESET_ASSERT                   = 0x1,
1574 } DCIO_DCRXPHY_SOFT_RESET;
1575 typedef enum DCIO_DPHY_LANE_SEL {
1576 	DCIO_DPHY_LANE_SEL_LANE0                         = 0x0,
1577 	DCIO_DPHY_LANE_SEL_LANE1                         = 0x1,
1578 	DCIO_DPHY_LANE_SEL_LANE2                         = 0x2,
1579 	DCIO_DPHY_LANE_SEL_LANE3                         = 0x3,
1580 } DCIO_DPHY_LANE_SEL;
1581 typedef enum DCIO_DPCS_INTERRUPT_TYPE {
1582 	DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED             = 0x0,
1583 	DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED             = 0x1,
1584 } DCIO_DPCS_INTERRUPT_TYPE;
1585 typedef enum DCIO_DPCS_INTERRUPT_MASK {
1586 	DCIO_DPCS_INTERRUPT_DISABLE                      = 0x0,
1587 	DCIO_DPCS_INTERRUPT_ENABLE                       = 0x1,
1588 } DCIO_DPCS_INTERRUPT_MASK;
1589 typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
1590 	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE     = 0x0,
1591 	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE     = 0x1,
1592 	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE     = 0x2,
1593 	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE     = 0x3,
1594 	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE     = 0x4,
1595 	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE     = 0x5,
1596 	DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE     = 0x6,
1597 	DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE     = 0x7,
1598 	DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE     = 0x8,
1599 	DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE     = 0x9,
1600 	DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE     = 0xa,
1601 	DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE     = 0xb,
1602 	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP       = 0xc,
1603 	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP       = 0xd,
1604 	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP       = 0xe,
1605 	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP       = 0xf,
1606 	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP       = 0x10,
1607 	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP       = 0x11,
1608 	DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP       = 0x12,
1609 	DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP       = 0x13,
1610 	DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP       = 0x14,
1611 	DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP       = 0x15,
1612 	DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP       = 0x16,
1613 	DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP       = 0x17,
1614 	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM    = 0x18,
1615 	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM    = 0x19,
1616 	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM    = 0x1a,
1617 	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM    = 0x1b,
1618 	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM    = 0x1c,
1619 	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM    = 0x1d,
1620 	DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM    = 0x1e,
1621 	DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM    = 0x1f,
1622 	DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM    = 0x20,
1623 	DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM    = 0x21,
1624 	DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM    = 0x22,
1625 	DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM    = 0x23,
1626 } DCIO_DC_GPU_TIMER_READ_SELECT;
1627 typedef enum DCIO_IMPCAL_STEP_DELAY {
1628 	DCIO_IMPCAL_STEP_DELAY_1us                       = 0x0,
1629 	DCIO_IMPCAL_STEP_DELAY_2us                       = 0x1,
1630 	DCIO_IMPCAL_STEP_DELAY_3us                       = 0x2,
1631 	DCIO_IMPCAL_STEP_DELAY_4us                       = 0x3,
1632 	DCIO_IMPCAL_STEP_DELAY_5us                       = 0x4,
1633 	DCIO_IMPCAL_STEP_DELAY_6us                       = 0x5,
1634 	DCIO_IMPCAL_STEP_DELAY_7us                       = 0x6,
1635 	DCIO_IMPCAL_STEP_DELAY_8us                       = 0x7,
1636 	DCIO_IMPCAL_STEP_DELAY_9us                       = 0x8,
1637 	DCIO_IMPCAL_STEP_DELAY_10us                      = 0x9,
1638 	DCIO_IMPCAL_STEP_DELAY_11us                      = 0xa,
1639 	DCIO_IMPCAL_STEP_DELAY_12us                      = 0xb,
1640 	DCIO_IMPCAL_STEP_DELAY_13us                      = 0xc,
1641 	DCIO_IMPCAL_STEP_DELAY_14us                      = 0xd,
1642 	DCIO_IMPCAL_STEP_DELAY_15us                      = 0xe,
1643 	DCIO_IMPCAL_STEP_DELAY_16us                      = 0xf,
1644 } DCIO_IMPCAL_STEP_DELAY;
1645 typedef enum DCIO_UNIPHY_IMPCAL_SEL {
1646 	DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE               = 0x0,
1647 	DCIO_UNIPHY_IMPCAL_SEL_BINARY                    = 0x1,
1648 } DCIO_UNIPHY_IMPCAL_SEL;
1649 typedef enum DCIO_DBG_CLOCK_SEL {
1650 	DCIO_DBG_CLOCK_SEL_DISPCLK                       = 0x0,
1651 	DCIO_DBG_CLOCK_SEL_SYMCLKA                       = 0x1,
1652 	DCIO_DBG_CLOCK_SEL_SYMCLKB                       = 0x2,
1653 	DCIO_DBG_CLOCK_SEL_SYMCLKC                       = 0x3,
1654 	DCIO_DBG_CLOCK_SEL_SYMCLKD                       = 0x4,
1655 	DCIO_DBG_CLOCK_SEL_SYMCLKE                       = 0x5,
1656 	DCIO_DBG_CLOCK_SEL_SYMCLKF                       = 0x6,
1657 	DCIO_DBG_CLOCK_SEL_REFCLK                        = 0xb,
1658 } DCIO_DBG_CLOCK_SEL;
1659 typedef enum DCIOCHIP_HPD_SEL {
1660 	DCIOCHIP_HPD_SEL_ASYNC                           = 0x0,
1661 	DCIOCHIP_HPD_SEL_CLOCKED                         = 0x1,
1662 } DCIOCHIP_HPD_SEL;
1663 typedef enum DCIOCHIP_PAD_MODE {
1664 	DCIOCHIP_PAD_MODE_DDC                            = 0x0,
1665 	DCIOCHIP_PAD_MODE_DP                             = 0x1,
1666 } DCIOCHIP_PAD_MODE;
1667 typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
1668 	DCIOCHIP_AUXSLAVE_PAD_MODE_I2C                   = 0x0,
1669 	DCIOCHIP_AUXSLAVE_PAD_MODE_AUX                   = 0x1,
1670 } DCIOCHIP_AUXSLAVE_PAD_MODE;
1671 typedef enum DCIOCHIP_INVERT {
1672 	DCIOCHIP_POL_NON_INVERT                          = 0x0,
1673 	DCIOCHIP_POL_INVERT                              = 0x1,
1674 } DCIOCHIP_INVERT;
1675 typedef enum DCIOCHIP_PD_EN {
1676 	DCIOCHIP_PD_EN_NOTALLOW                          = 0x0,
1677 	DCIOCHIP_PD_EN_ALLOW                             = 0x1,
1678 } DCIOCHIP_PD_EN;
1679 typedef enum DCIOCHIP_GPIO_MASK_EN {
1680 	DCIOCHIP_GPIO_MASK_EN_HARDWARE                   = 0x0,
1681 	DCIOCHIP_GPIO_MASK_EN_SOFTWARE                   = 0x1,
1682 } DCIOCHIP_GPIO_MASK_EN;
1683 typedef enum DCIOCHIP_MASK {
1684 	DCIOCHIP_MASK_DISABLE                            = 0x0,
1685 	DCIOCHIP_MASK_ENABLE                             = 0x1,
1686 } DCIOCHIP_MASK;
1687 typedef enum DCIOCHIP_GPIO_I2C_MASK {
1688 	DCIOCHIP_GPIO_I2C_MASK_DISABLE                   = 0x0,
1689 	DCIOCHIP_GPIO_I2C_MASK_ENABLE                    = 0x1,
1690 } DCIOCHIP_GPIO_I2C_MASK;
1691 typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
1692 	DCIOCHIP_GPIO_I2C_DRIVE_LOW                      = 0x0,
1693 	DCIOCHIP_GPIO_I2C_DRIVE_HIGH                     = 0x1,
1694 } DCIOCHIP_GPIO_I2C_DRIVE;
1695 typedef enum DCIOCHIP_GPIO_I2C_EN {
1696 	DCIOCHIP_GPIO_I2C_DISABLE                        = 0x0,
1697 	DCIOCHIP_GPIO_I2C_ENABLE                         = 0x1,
1698 } DCIOCHIP_GPIO_I2C_EN;
1699 typedef enum DCIOCHIP_MASK_4BIT {
1700 	DCIOCHIP_MASK_4BIT_DISABLE                       = 0x0,
1701 	DCIOCHIP_MASK_4BIT_ENABLE                        = 0xf,
1702 } DCIOCHIP_MASK_4BIT;
1703 typedef enum DCIOCHIP_ENABLE_4BIT {
1704 	DCIOCHIP_4BIT_DISABLE                            = 0x0,
1705 	DCIOCHIP_4BIT_ENABLE                             = 0xf,
1706 } DCIOCHIP_ENABLE_4BIT;
1707 typedef enum DCIOCHIP_MASK_5BIT {
1708 	DCIOCHIP_MASIK_5BIT_DISABLE                      = 0x0,
1709 	DCIOCHIP_MASIK_5BIT_ENABLE                       = 0x1f,
1710 } DCIOCHIP_MASK_5BIT;
1711 typedef enum DCIOCHIP_ENABLE_5BIT {
1712 	DCIOCHIP_5BIT_DISABLE                            = 0x0,
1713 	DCIOCHIP_5BIT_ENABLE                             = 0x1f,
1714 } DCIOCHIP_ENABLE_5BIT;
1715 typedef enum DCIOCHIP_MASK_2BIT {
1716 	DCIOCHIP_MASK_2BIT_DISABLE                       = 0x0,
1717 	DCIOCHIP_MASK_2BIT_ENABLE                        = 0x3,
1718 } DCIOCHIP_MASK_2BIT;
1719 typedef enum DCIOCHIP_ENABLE_2BIT {
1720 	DCIOCHIP_2BIT_DISABLE                            = 0x0,
1721 	DCIOCHIP_2BIT_ENABLE                             = 0x3,
1722 } DCIOCHIP_ENABLE_2BIT;
1723 typedef enum DCIOCHIP_REF_27_SRC_SEL {
1724 	DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER             = 0x0,
1725 	DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER      = 0x1,
1726 	DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS              = 0x2,
1727 	DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS       = 0x3,
1728 } DCIOCHIP_REF_27_SRC_SEL;
1729 typedef enum DCIOCHIP_DVO_VREFPON {
1730 	DCIOCHIP_DVO_VREFPON_DISABLE                     = 0x0,
1731 	DCIOCHIP_DVO_VREFPON_ENABLE                      = 0x1,
1732 } DCIOCHIP_DVO_VREFPON;
1733 typedef enum DCIOCHIP_DVO_VREFSEL {
1734 	DCIOCHIP_DVO_VREFSEL_ONCHIP                      = 0x0,
1735 	DCIOCHIP_DVO_VREFSEL_EXTERNAL                    = 0x1,
1736 } DCIOCHIP_DVO_VREFSEL;
1737 typedef enum DCIOCHIP_SPDIF1_IMODE {
1738 	DCIOCHIP_SPDIF1_IMODE_OE_A                       = 0x0,
1739 	DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO                  = 0x1,
1740 } DCIOCHIP_SPDIF1_IMODE;
1741 typedef enum DCIOCHIP_AUX_FALLSLEWSEL {
1742 	DCIOCHIP_AUX_FALLSLEWSEL_LOW                     = 0x0,
1743 	DCIOCHIP_AUX_FALLSLEWSEL_HIGH0                   = 0x1,
1744 	DCIOCHIP_AUX_FALLSLEWSEL_HIGH1                   = 0x2,
1745 	DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH               = 0x3,
1746 } DCIOCHIP_AUX_FALLSLEWSEL;
1747 typedef enum DCIOCHIP_AUX_SPIKESEL {
1748 	DCIOCHIP_AUX_SPIKESEL_50NS                       = 0x0,
1749 	DCIOCHIP_AUX_SPIKESEL_10NS                       = 0x1,
1750 } DCIOCHIP_AUX_SPIKESEL;
1751 typedef enum DCIOCHIP_AUX_CSEL0P9 {
1752 	DCIOCHIP_AUX_CSEL_DEC1P0                         = 0x0,
1753 	DCIOCHIP_AUX_CSEL_DEC0P9                         = 0x1,
1754 } DCIOCHIP_AUX_CSEL0P9;
1755 typedef enum DCIOCHIP_AUX_CSEL1P1 {
1756 	DCIOCHIP_AUX_CSEL_INC1P0                         = 0x0,
1757 	DCIOCHIP_AUX_CSEL_INC1P1                         = 0x1,
1758 } DCIOCHIP_AUX_CSEL1P1;
1759 typedef enum DCIOCHIP_AUX_RSEL0P9 {
1760 	DCIOCHIP_AUX_RSEL_DEC1P0                         = 0x0,
1761 	DCIOCHIP_AUX_RSEL_DEC0P9                         = 0x1,
1762 } DCIOCHIP_AUX_RSEL0P9;
1763 typedef enum DCIOCHIP_AUX_RSEL1P1 {
1764 	DCIOCHIP_AUX_RSEL_INC1P0                         = 0x0,
1765 	DCIOCHIP_AUX_RSEL_INC1P1                         = 0x1,
1766 } DCIOCHIP_AUX_RSEL1P1;
1767 typedef enum DCP_GRPH_ENABLE {
1768 	DCP_GRPH_ENABLE_FALSE                            = 0x0,
1769 	DCP_GRPH_ENABLE_TRUE                             = 0x1,
1770 } DCP_GRPH_ENABLE;
1771 typedef enum DCP_GRPH_KEYER_ALPHA_SEL {
1772 	DCP_GRPH_KEYER_ALPHA_SEL_FALSE                   = 0x0,
1773 	DCP_GRPH_KEYER_ALPHA_SEL_TRUE                    = 0x1,
1774 } DCP_GRPH_KEYER_ALPHA_SEL;
1775 typedef enum DCP_GRPH_DEPTH {
1776 	DCP_GRPH_DEPTH_8BPP                              = 0x0,
1777 	DCP_GRPH_DEPTH_16BPP                             = 0x1,
1778 	DCP_GRPH_DEPTH_32BPP                             = 0x2,
1779 	DCP_GRPH_DEPTH_64BPP                             = 0x3,
1780 } DCP_GRPH_DEPTH;
1781 typedef enum DCP_GRPH_NUM_BANKS {
1782 	DCP_GRPH_NUM_BANKS_2BANK                         = 0x0,
1783 	DCP_GRPH_NUM_BANKS_4BANK                         = 0x1,
1784 	DCP_GRPH_NUM_BANKS_8BANK                         = 0x2,
1785 	DCP_GRPH_NUM_BANKS_16BANK                        = 0x3,
1786 } DCP_GRPH_NUM_BANKS;
1787 typedef enum DCP_GRPH_BANK_WIDTH {
1788 	DCP_GRPH_BANK_WIDTH_1                            = 0x0,
1789 	DCP_GRPH_BANK_WIDTH_2                            = 0x1,
1790 	DCP_GRPH_BANK_WIDTH_4                            = 0x2,
1791 	DCP_GRPH_BANK_WIDTH_8                            = 0x3,
1792 } DCP_GRPH_BANK_WIDTH;
1793 typedef enum DCP_GRPH_FORMAT {
1794 	DCP_GRPH_FORMAT_8BPP                             = 0x0,
1795 	DCP_GRPH_FORMAT_16BPP                            = 0x1,
1796 	DCP_GRPH_FORMAT_32BPP                            = 0x2,
1797 	DCP_GRPH_FORMAT_64BPP                            = 0x3,
1798 } DCP_GRPH_FORMAT;
1799 typedef enum DCP_GRPH_BANK_HEIGHT {
1800 	DCP_GRPH_BANK_HEIGHT_1                           = 0x0,
1801 	DCP_GRPH_BANK_HEIGHT_2                           = 0x1,
1802 	DCP_GRPH_BANK_HEIGHT_4                           = 0x2,
1803 	DCP_GRPH_BANK_HEIGHT_8                           = 0x3,
1804 } DCP_GRPH_BANK_HEIGHT;
1805 typedef enum DCP_GRPH_TILE_SPLIT {
1806 	DCP_GRPH_TILE_SPLIT_64B                          = 0x0,
1807 	DCP_GRPH_TILE_SPLIT_128B                         = 0x1,
1808 	DCP_GRPH_TILE_SPLIT_256B                         = 0x2,
1809 	DCP_GRPH_TILE_SPLIT_512B                         = 0x3,
1810 	DCP_GRPH_TILE_SPLIT_1B                           = 0x4,
1811 	DCP_GRPH_TILE_SPLIT_2B                           = 0x5,
1812 	DCP_GRPH_TILE_SPLIT_4B                           = 0x6,
1813 } DCP_GRPH_TILE_SPLIT;
1814 typedef enum DCP_GRPH_ADDRESS_TRANSLATION_ENABLE {
1815 	DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE        = 0x0,
1816 	DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE         = 0x1,
1817 } DCP_GRPH_ADDRESS_TRANSLATION_ENABLE;
1818 typedef enum DCP_GRPH_PRIVILEGED_ACCESS_ENABLE {
1819 	DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_FALSE          = 0x0,
1820 	DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_TRUE           = 0x1,
1821 } DCP_GRPH_PRIVILEGED_ACCESS_ENABLE;
1822 typedef enum DCP_GRPH_MACRO_TILE_ASPECT {
1823 	DCP_GRPH_MACRO_TILE_ASPECT_1                     = 0x0,
1824 	DCP_GRPH_MACRO_TILE_ASPECT_2                     = 0x1,
1825 	DCP_GRPH_MACRO_TILE_ASPECT_4                     = 0x2,
1826 	DCP_GRPH_MACRO_TILE_ASPECT_8                     = 0x3,
1827 } DCP_GRPH_MACRO_TILE_ASPECT;
1828 typedef enum DCP_GRPH_ARRAY_MODE {
1829 	DCP_GRPH_ARRAY_MODE_0                            = 0x0,
1830 	DCP_GRPH_ARRAY_MODE_1                            = 0x1,
1831 	DCP_GRPH_ARRAY_MODE_2                            = 0x2,
1832 	DCP_GRPH_ARRAY_MODE_3                            = 0x3,
1833 	DCP_GRPH_ARRAY_MODE_4                            = 0x4,
1834 	DCP_GRPH_ARRAY_MODE_7                            = 0x7,
1835 	DCP_GRPH_ARRAY_MODE_12                           = 0xc,
1836 	DCP_GRPH_ARRAY_MODE_13                           = 0xd,
1837 } DCP_GRPH_ARRAY_MODE;
1838 typedef enum DCP_GRPH_MICRO_TILE_MODE {
1839 	DCP_GRPH_MICRO_TILE_MODE_0                       = 0x0,
1840 	DCP_GRPH_MICRO_TILE_MODE_1                       = 0x1,
1841 	DCP_GRPH_MICRO_TILE_MODE_2                       = 0x2,
1842 	DCP_GRPH_MICRO_TILE_MODE_3                       = 0x3,
1843 } DCP_GRPH_MICRO_TILE_MODE;
1844 typedef enum DCP_GRPH_COLOR_EXPANSION_MODE {
1845 	DCP_GRPH_COLOR_EXPANSION_MODE_DEXP               = 0x0,
1846 	DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP               = 0x1,
1847 } DCP_GRPH_COLOR_EXPANSION_MODE;
1848 typedef enum DCP_GRPH_LUT_10BIT_BYPASS_EN {
1849 	DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE               = 0x0,
1850 	DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE                = 0x1,
1851 } DCP_GRPH_LUT_10BIT_BYPASS_EN;
1852 typedef enum DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN {
1853 	DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE       = 0x0,
1854 	DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE        = 0x1,
1855 } DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN;
1856 typedef enum DCP_GRPH_ENDIAN_SWAP {
1857 	DCP_GRPH_ENDIAN_SWAP_NONE                        = 0x0,
1858 	DCP_GRPH_ENDIAN_SWAP_8IN16                       = 0x1,
1859 	DCP_GRPH_ENDIAN_SWAP_8IN32                       = 0x2,
1860 	DCP_GRPH_ENDIAN_SWAP_8IN64                       = 0x3,
1861 } DCP_GRPH_ENDIAN_SWAP;
1862 typedef enum DCP_GRPH_RED_CROSSBAR {
1863 	DCP_GRPH_RED_CROSSBAR_FROM_R                     = 0x0,
1864 	DCP_GRPH_RED_CROSSBAR_FROM_G                     = 0x1,
1865 	DCP_GRPH_RED_CROSSBAR_FROM_B                     = 0x2,
1866 	DCP_GRPH_RED_CROSSBAR_FROM_A                     = 0x3,
1867 } DCP_GRPH_RED_CROSSBAR;
1868 typedef enum DCP_GRPH_GREEN_CROSSBAR {
1869 	DCP_GRPH_GREEN_CROSSBAR_FROM_G                   = 0x0,
1870 	DCP_GRPH_GREEN_CROSSBAR_FROM_B                   = 0x1,
1871 	DCP_GRPH_GREEN_CROSSBAR_FROM_A                   = 0x2,
1872 	DCP_GRPH_GREEN_CROSSBAR_FROM_R                   = 0x3,
1873 } DCP_GRPH_GREEN_CROSSBAR;
1874 typedef enum DCP_GRPH_BLUE_CROSSBAR {
1875 	DCP_GRPH_BLUE_CROSSBAR_FROM_B                    = 0x0,
1876 	DCP_GRPH_BLUE_CROSSBAR_FROM_A                    = 0x1,
1877 	DCP_GRPH_BLUE_CROSSBAR_FROM_R                    = 0x2,
1878 	DCP_GRPH_BLUE_CROSSBAR_FROM_G                    = 0x3,
1879 } DCP_GRPH_BLUE_CROSSBAR;
1880 typedef enum DCP_GRPH_ALPHA_CROSSBAR {
1881 	DCP_GRPH_ALPHA_CROSSBAR_FROM_A                   = 0x0,
1882 	DCP_GRPH_ALPHA_CROSSBAR_FROM_R                   = 0x1,
1883 	DCP_GRPH_ALPHA_CROSSBAR_FROM_G                   = 0x2,
1884 	DCP_GRPH_ALPHA_CROSSBAR_FROM_B                   = 0x3,
1885 } DCP_GRPH_ALPHA_CROSSBAR;
1886 typedef enum DCP_GRPH_PRIMARY_DFQ_ENABLE {
1887 	DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE                = 0x0,
1888 	DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE                 = 0x1,
1889 } DCP_GRPH_PRIMARY_DFQ_ENABLE;
1890 typedef enum DCP_GRPH_SECONDARY_DFQ_ENABLE {
1891 	DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE              = 0x0,
1892 	DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE               = 0x1,
1893 } DCP_GRPH_SECONDARY_DFQ_ENABLE;
1894 typedef enum DCP_GRPH_INPUT_GAMMA_MODE {
1895 	DCP_GRPH_INPUT_GAMMA_MODE_LUT                    = 0x0,
1896 	DCP_GRPH_INPUT_GAMMA_MODE_BYPASS                 = 0x1,
1897 } DCP_GRPH_INPUT_GAMMA_MODE;
1898 typedef enum DCP_GRPH_MODE_UPDATE_PENDING {
1899 	DCP_GRPH_MODE_UPDATE_PENDING_FALSE               = 0x0,
1900 	DCP_GRPH_MODE_UPDATE_PENDING_TRUE                = 0x1,
1901 } DCP_GRPH_MODE_UPDATE_PENDING;
1902 typedef enum DCP_GRPH_MODE_UPDATE_TAKEN {
1903 	DCP_GRPH_MODE_UPDATE_TAKEN_FALSE                 = 0x0,
1904 	DCP_GRPH_MODE_UPDATE_TAKEN_TRUE                  = 0x1,
1905 } DCP_GRPH_MODE_UPDATE_TAKEN;
1906 typedef enum DCP_GRPH_SURFACE_UPDATE_PENDING {
1907 	DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE            = 0x0,
1908 	DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE             = 0x1,
1909 } DCP_GRPH_SURFACE_UPDATE_PENDING;
1910 typedef enum DCP_GRPH_SURFACE_UPDATE_TAKEN {
1911 	DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE              = 0x0,
1912 	DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE               = 0x1,
1913 } DCP_GRPH_SURFACE_UPDATE_TAKEN;
1914 typedef enum DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE {
1915 	DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE       = 0x0,
1916 	DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE        = 0x1,
1917 } DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE;
1918 typedef enum DCP_GRPH_UPDATE_LOCK {
1919 	DCP_GRPH_UPDATE_LOCK_FALSE                       = 0x0,
1920 	DCP_GRPH_UPDATE_LOCK_TRUE                        = 0x1,
1921 } DCP_GRPH_UPDATE_LOCK;
1922 typedef enum DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
1923 	DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE        = 0x0,
1924 	DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE         = 0x1,
1925 } DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
1926 typedef enum DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
1927 	DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE      = 0x0,
1928 	DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE       = 0x1,
1929 } DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
1930 typedef enum DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
1931 	DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE   = 0x0,
1932 	DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE    = 0x1,
1933 } DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
1934 typedef enum DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN {
1935 	DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE       = 0x0,
1936 	DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE        = 0x1,
1937 } DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1938 typedef enum DCP_GRPH_XDMA_SUPER_AA_EN {
1939 	DCP_GRPH_XDMA_SUPER_AA_EN_FALSE                  = 0x0,
1940 	DCP_GRPH_XDMA_SUPER_AA_EN_TRUE                   = 0x1,
1941 } DCP_GRPH_XDMA_SUPER_AA_EN;
1942 typedef enum DCP_GRPH_DFQ_RESET {
1943 	DCP_GRPH_DFQ_RESET_FALSE                         = 0x0,
1944 	DCP_GRPH_DFQ_RESET_TRUE                          = 0x1,
1945 } DCP_GRPH_DFQ_RESET;
1946 typedef enum DCP_GRPH_DFQ_SIZE {
1947 	DCP_GRPH_DFQ_SIZE_DEEP1                          = 0x0,
1948 	DCP_GRPH_DFQ_SIZE_DEEP2                          = 0x1,
1949 	DCP_GRPH_DFQ_SIZE_DEEP3                          = 0x2,
1950 	DCP_GRPH_DFQ_SIZE_DEEP4                          = 0x3,
1951 	DCP_GRPH_DFQ_SIZE_DEEP5                          = 0x4,
1952 	DCP_GRPH_DFQ_SIZE_DEEP6                          = 0x5,
1953 	DCP_GRPH_DFQ_SIZE_DEEP7                          = 0x6,
1954 	DCP_GRPH_DFQ_SIZE_DEEP8                          = 0x7,
1955 } DCP_GRPH_DFQ_SIZE;
1956 typedef enum DCP_GRPH_DFQ_MIN_FREE_ENTRIES {
1957 	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1                  = 0x0,
1958 	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2                  = 0x1,
1959 	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3                  = 0x2,
1960 	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4                  = 0x3,
1961 	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5                  = 0x4,
1962 	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6                  = 0x5,
1963 	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7                  = 0x6,
1964 	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8                  = 0x7,
1965 } DCP_GRPH_DFQ_MIN_FREE_ENTRIES;
1966 typedef enum DCP_GRPH_DFQ_RESET_ACK {
1967 	DCP_GRPH_DFQ_RESET_ACK_FALSE                     = 0x0,
1968 	DCP_GRPH_DFQ_RESET_ACK_TRUE                      = 0x1,
1969 } DCP_GRPH_DFQ_RESET_ACK;
1970 typedef enum DCP_GRPH_PFLIP_INT_CLEAR {
1971 	DCP_GRPH_PFLIP_INT_CLEAR_FALSE                   = 0x0,
1972 	DCP_GRPH_PFLIP_INT_CLEAR_TRUE                    = 0x1,
1973 } DCP_GRPH_PFLIP_INT_CLEAR;
1974 typedef enum DCP_GRPH_PFLIP_INT_MASK {
1975 	DCP_GRPH_PFLIP_INT_MASK_FALSE                    = 0x0,
1976 	DCP_GRPH_PFLIP_INT_MASK_TRUE                     = 0x1,
1977 } DCP_GRPH_PFLIP_INT_MASK;
1978 typedef enum DCP_GRPH_PFLIP_INT_TYPE {
1979 	DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL             = 0x0,
1980 	DCP_GRPH_PFLIP_INT_TYPE_PULSE                    = 0x1,
1981 } DCP_GRPH_PFLIP_INT_TYPE;
1982 typedef enum DCP_GRPH_PRESCALE_SELECT {
1983 	DCP_GRPH_PRESCALE_SELECT_FIXED                   = 0x0,
1984 	DCP_GRPH_PRESCALE_SELECT_FLOATING                = 0x1,
1985 } DCP_GRPH_PRESCALE_SELECT;
1986 typedef enum DCP_GRPH_PRESCALE_R_SIGN {
1987 	DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED                = 0x0,
1988 	DCP_GRPH_PRESCALE_R_SIGN_SIGNED                  = 0x1,
1989 } DCP_GRPH_PRESCALE_R_SIGN;
1990 typedef enum DCP_GRPH_PRESCALE_G_SIGN {
1991 	DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED                = 0x0,
1992 	DCP_GRPH_PRESCALE_G_SIGN_SIGNED                  = 0x1,
1993 } DCP_GRPH_PRESCALE_G_SIGN;
1994 typedef enum DCP_GRPH_PRESCALE_B_SIGN {
1995 	DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED                = 0x0,
1996 	DCP_GRPH_PRESCALE_B_SIGN_SIGNED                  = 0x1,
1997 } DCP_GRPH_PRESCALE_B_SIGN;
1998 typedef enum DCP_GRPH_PRESCALE_BYPASS {
1999 	DCP_GRPH_PRESCALE_BYPASS_FALSE                   = 0x0,
2000 	DCP_GRPH_PRESCALE_BYPASS_TRUE                    = 0x1,
2001 } DCP_GRPH_PRESCALE_BYPASS;
2002 typedef enum DCP_INPUT_CSC_GRPH_MODE {
2003 	DCP_INPUT_CSC_GRPH_MODE_BYPASS                   = 0x0,
2004 	DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF           = 0x1,
2005 	DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF              = 0x2,
2006 	DCP_INPUT_CSC_GRPH_MODE_RESERVED                 = 0x3,
2007 } DCP_INPUT_CSC_GRPH_MODE;
2008 typedef enum DCP_OUTPUT_CSC_GRPH_MODE {
2009 	DCP_OUTPUT_CSC_GRPH_MODE_BYPASS                  = 0x0,
2010 	DCP_OUTPUT_CSC_GRPH_MODE_RGB                     = 0x1,
2011 	DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601                = 0x2,
2012 	DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709                = 0x3,
2013 	DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF         = 0x4,
2014 	DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF             = 0x5,
2015 	DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0               = 0x6,
2016 	DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1               = 0x7,
2017 } DCP_OUTPUT_CSC_GRPH_MODE;
2018 typedef enum DCP_DENORM_MODE {
2019 	DCP_DENORM_MODE_UNITY                            = 0x0,
2020 	DCP_DENORM_MODE_6BIT                             = 0x1,
2021 	DCP_DENORM_MODE_8BIT                             = 0x2,
2022 	DCP_DENORM_MODE_10BIT                            = 0x3,
2023 	DCP_DENORM_MODE_11BIT                            = 0x4,
2024 	DCP_DENORM_MODE_12BIT                            = 0x5,
2025 	DCP_DENORM_MODE_RESERVED0                        = 0x6,
2026 	DCP_DENORM_MODE_RESERVED1                        = 0x7,
2027 } DCP_DENORM_MODE;
2028 typedef enum DCP_DENORM_14BIT_OUT {
2029 	DCP_DENORM_14BIT_OUT_FALSE                       = 0x0,
2030 	DCP_DENORM_14BIT_OUT_TRUE                        = 0x1,
2031 } DCP_DENORM_14BIT_OUT;
2032 typedef enum DCP_OUT_ROUND_TRUNC_MODE {
2033 	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12             = 0x0,
2034 	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11             = 0x1,
2035 	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10             = 0x2,
2036 	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9              = 0x3,
2037 	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8              = 0x4,
2038 	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED       = 0x5,
2039 	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14             = 0x6,
2040 	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13             = 0x7,
2041 	DCP_OUT_ROUND_TRUNC_MODE_ROUND_12                = 0x8,
2042 	DCP_OUT_ROUND_TRUNC_MODE_ROUND_11                = 0x9,
2043 	DCP_OUT_ROUND_TRUNC_MODE_ROUND_10                = 0xa,
2044 	DCP_OUT_ROUND_TRUNC_MODE_ROUND_9                 = 0xb,
2045 	DCP_OUT_ROUND_TRUNC_MODE_ROUND_8                 = 0xc,
2046 	DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED          = 0xd,
2047 	DCP_OUT_ROUND_TRUNC_MODE_ROUND_14                = 0xe,
2048 	DCP_OUT_ROUND_TRUNC_MODE_ROUND_13                = 0xf,
2049 } DCP_OUT_ROUND_TRUNC_MODE;
2050 typedef enum DCP_KEY_MODE {
2051 	DCP_KEY_MODE_ALPHA0                              = 0x0,
2052 	DCP_KEY_MODE_ALPHA1                              = 0x1,
2053 	DCP_KEY_MODE_IN_RANGE_ALPHA1                     = 0x2,
2054 	DCP_KEY_MODE_IN_RANGE_ALPHA0                     = 0x3,
2055 } DCP_KEY_MODE;
2056 typedef enum DCP_GRPH_DEGAMMA_MODE {
2057 	DCP_GRPH_DEGAMMA_MODE_BYPASS                     = 0x0,
2058 	DCP_GRPH_DEGAMMA_MODE_ROMA                       = 0x1,
2059 	DCP_GRPH_DEGAMMA_MODE_ROMB                       = 0x2,
2060 	DCP_GRPH_DEGAMMA_MODE_RESERVED                   = 0x3,
2061 } DCP_GRPH_DEGAMMA_MODE;
2062 typedef enum DCP_CURSOR2_DEGAMMA_MODE {
2063 	DCP_CURSOR2_DEGAMMA_MODE_BYPASS                  = 0x0,
2064 	DCP_CURSOR2_DEGAMMA_MODE_ROMA                    = 0x1,
2065 	DCP_CURSOR2_DEGAMMA_MODE_ROMB                    = 0x2,
2066 	DCP_CURSOR2_DEGAMMA_MODE_RESERVED                = 0x3,
2067 } DCP_CURSOR2_DEGAMMA_MODE;
2068 typedef enum DCP_CURSOR_DEGAMMA_MODE {
2069 	DCP_CURSOR_DEGAMMA_MODE_BYPASS                   = 0x0,
2070 	DCP_CURSOR_DEGAMMA_MODE_ROMA                     = 0x1,
2071 	DCP_CURSOR_DEGAMMA_MODE_ROMB                     = 0x2,
2072 	DCP_CURSOR_DEGAMMA_MODE_RESERVED                 = 0x3,
2073 } DCP_CURSOR_DEGAMMA_MODE;
2074 typedef enum DCP_GRPH_GAMUT_REMAP_MODE {
2075 	DCP_GRPH_GAMUT_REMAP_MODE_BYPASS                 = 0x0,
2076 	DCP_GRPH_GAMUT_REMAP_MODE_ROMA                   = 0x1,
2077 	DCP_GRPH_GAMUT_REMAP_MODE_ROMB                   = 0x2,
2078 	DCP_GRPH_GAMUT_REMAP_MODE_RESERVED               = 0x3,
2079 } DCP_GRPH_GAMUT_REMAP_MODE;
2080 typedef enum DCP_SPATIAL_DITHER_EN {
2081 	DCP_SPATIAL_DITHER_EN_FALSE                      = 0x0,
2082 	DCP_SPATIAL_DITHER_EN_TRUE                       = 0x1,
2083 } DCP_SPATIAL_DITHER_EN;
2084 typedef enum DCP_SPATIAL_DITHER_MODE {
2085 	DCP_SPATIAL_DITHER_MODE_BYPASS                   = 0x0,
2086 	DCP_SPATIAL_DITHER_MODE_ROMA                     = 0x1,
2087 	DCP_SPATIAL_DITHER_MODE_ROMB                     = 0x2,
2088 	DCP_SPATIAL_DITHER_MODE_RESERVED                 = 0x3,
2089 } DCP_SPATIAL_DITHER_MODE;
2090 typedef enum DCP_SPATIAL_DITHER_DEPTH {
2091 	DCP_SPATIAL_DITHER_DEPTH_30BPP                   = 0x0,
2092 	DCP_SPATIAL_DITHER_DEPTH_24BPP                   = 0x1,
2093 	DCP_SPATIAL_DITHER_DEPTH_36BPP                   = 0x2,
2094 	DCP_SPATIAL_DITHER_DEPTH_UNDEFINED               = 0x3,
2095 } DCP_SPATIAL_DITHER_DEPTH;
2096 typedef enum DCP_FRAME_RANDOM_ENABLE {
2097 	DCP_FRAME_RANDOM_ENABLE_FALSE                    = 0x0,
2098 	DCP_FRAME_RANDOM_ENABLE_TRUE                     = 0x1,
2099 } DCP_FRAME_RANDOM_ENABLE;
2100 typedef enum DCP_RGB_RANDOM_ENABLE {
2101 	DCP_RGB_RANDOM_ENABLE_FALSE                      = 0x0,
2102 	DCP_RGB_RANDOM_ENABLE_TRUE                       = 0x1,
2103 } DCP_RGB_RANDOM_ENABLE;
2104 typedef enum DCP_HIGHPASS_RANDOM_ENABLE {
2105 	DCP_HIGHPASS_RANDOM_ENABLE_FALSE                 = 0x0,
2106 	DCP_HIGHPASS_RANDOM_ENABLE_TRUE                  = 0x1,
2107 } DCP_HIGHPASS_RANDOM_ENABLE;
2108 typedef enum DCP_CURSOR_EN {
2109 	DCP_CURSOR_EN_FALSE                              = 0x0,
2110 	DCP_CURSOR_EN_TRUE                               = 0x1,
2111 } DCP_CURSOR_EN;
2112 typedef enum DCP_CUR_INV_TRANS_CLAMP {
2113 	DCP_CUR_INV_TRANS_CLAMP_FALSE                    = 0x0,
2114 	DCP_CUR_INV_TRANS_CLAMP_TRUE                     = 0x1,
2115 } DCP_CUR_INV_TRANS_CLAMP;
2116 typedef enum DCP_CURSOR_MODE {
2117 	DCP_CURSOR_MODE_MONO_2BPP                        = 0x0,
2118 	DCP_CURSOR_MODE_24BPP_1BIT                       = 0x1,
2119 	DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI              = 0x2,
2120 	DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI            = 0x3,
2121 } DCP_CURSOR_MODE;
2122 typedef enum DCP_CURSOR_2X_MAGNIFY {
2123 	DCP_CURSOR_2X_MAGNIFY_FALSE                      = 0x0,
2124 	DCP_CURSOR_2X_MAGNIFY_TRUE                       = 0x1,
2125 } DCP_CURSOR_2X_MAGNIFY;
2126 typedef enum DCP_CURSOR_FORCE_MC_ON {
2127 	DCP_CURSOR_FORCE_MC_ON_FALSE                     = 0x0,
2128 	DCP_CURSOR_FORCE_MC_ON_TRUE                      = 0x1,
2129 } DCP_CURSOR_FORCE_MC_ON;
2130 typedef enum DCP_CURSOR_URGENT_CONTROL {
2131 	DCP_CURSOR_URGENT_CONTROL_MODE_0                 = 0x0,
2132 	DCP_CURSOR_URGENT_CONTROL_MODE_1                 = 0x1,
2133 	DCP_CURSOR_URGENT_CONTROL_MODE_2                 = 0x2,
2134 	DCP_CURSOR_URGENT_CONTROL_MODE_3                 = 0x3,
2135 	DCP_CURSOR_URGENT_CONTROL_MODE_4                 = 0x4,
2136 } DCP_CURSOR_URGENT_CONTROL;
2137 typedef enum DCP_CURSOR_UPDATE_PENDING {
2138 	DCP_CURSOR_UPDATE_PENDING_FALSE                  = 0x0,
2139 	DCP_CURSOR_UPDATE_PENDING_TRUE                   = 0x1,
2140 } DCP_CURSOR_UPDATE_PENDING;
2141 typedef enum DCP_CURSOR_UPDATE_TAKEN {
2142 	DCP_CURSOR_UPDATE_TAKEN_FALSE                    = 0x0,
2143 	DCP_CURSOR_UPDATE_TAKEN_TRUE                     = 0x1,
2144 } DCP_CURSOR_UPDATE_TAKEN;
2145 typedef enum DCP_CURSOR_UPDATE_LOCK {
2146 	DCP_CURSOR_UPDATE_LOCK_FALSE                     = 0x0,
2147 	DCP_CURSOR_UPDATE_LOCK_TRUE                      = 0x1,
2148 } DCP_CURSOR_UPDATE_LOCK;
2149 typedef enum DCP_CURSOR_DISABLE_MULTIPLE_UPDATE {
2150 	DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE         = 0x0,
2151 	DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE          = 0x1,
2152 } DCP_CURSOR_DISABLE_MULTIPLE_UPDATE;
2153 typedef enum DCP_CURSOR_UPDATE_STEREO_MODE {
2154 	DCP_CURSOR_UPDATE_STEREO_MODE_BOTH               = 0x0,
2155 	DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY     = 0x1,
2156 	DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED          = 0x2,
2157 	DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY       = 0x3,
2158 } DCP_CURSOR_UPDATE_STEREO_MODE;
2159 typedef enum DCP_CURSOR2_EN {
2160 	DCP_CURSOR2_EN_FALSE                             = 0x0,
2161 	DCP_CURSOR2_EN_TRUE                              = 0x1,
2162 } DCP_CURSOR2_EN;
2163 typedef enum DCP_CUR2_INV_TRANS_CLAMP {
2164 	DCP_CUR2_INV_TRANS_CLAMP_FALSE                   = 0x0,
2165 	DCP_CUR2_INV_TRANS_CLAMP_TRUE                    = 0x1,
2166 } DCP_CUR2_INV_TRANS_CLAMP;
2167 typedef enum DCP_CURSOR2_MODE {
2168 	DCP_CURSOR2_MODE_MONO_2BPP                       = 0x0,
2169 	DCP_CURSOR2_MODE_24BPP_1BIT                      = 0x1,
2170 	DCP_CURSOR2_MODE_24BPP_8BIT_PREMULTI             = 0x2,
2171 	DCP_CURSOR2_MODE_24BPP_8BIT_UNPREMULTI           = 0x3,
2172 } DCP_CURSOR2_MODE;
2173 typedef enum DCP_CURSOR2_2X_MAGNIFY {
2174 	DCP_CURSOR2_2X_MAGNIFY_FALSE                     = 0x0,
2175 	DCP_CURSOR2_2X_MAGNIFY_TRUE                      = 0x1,
2176 } DCP_CURSOR2_2X_MAGNIFY;
2177 typedef enum DCP_CURSOR2_FORCE_MC_ON {
2178 	DCP_CURSOR2_FORCE_MC_ON_FALSE                    = 0x0,
2179 	DCP_CURSOR2_FORCE_MC_ON_TRUE                     = 0x1,
2180 } DCP_CURSOR2_FORCE_MC_ON;
2181 typedef enum DCP_CURSOR2_URGENT_CONTROL {
2182 	DCP_CURSOR2_URGENT_CONTROL_MODE_0                = 0x0,
2183 	DCP_CURSOR2_URGENT_CONTROL_MODE_1                = 0x1,
2184 	DCP_CURSOR2_URGENT_CONTROL_MODE_2                = 0x2,
2185 	DCP_CURSOR2_URGENT_CONTROL_MODE_3                = 0x3,
2186 	DCP_CURSOR2_URGENT_CONTROL_MODE_4                = 0x4,
2187 } DCP_CURSOR2_URGENT_CONTROL;
2188 typedef enum DCP_CURSOR2_UPDATE_PENDING {
2189 	DCP_CURSOR2_UPDATE_PENDING_FALSE                 = 0x0,
2190 	DCP_CURSOR2_UPDATE_PENDING_TRUE                  = 0x1,
2191 } DCP_CURSOR2_UPDATE_PENDING;
2192 typedef enum DCP_CURSOR2_UPDATE_TAKEN {
2193 	DCP_CURSOR2_UPDATE_TAKEN_FALSE                   = 0x0,
2194 	DCP_CURSOR2_UPDATE_TAKEN_TRUE                    = 0x1,
2195 } DCP_CURSOR2_UPDATE_TAKEN;
2196 typedef enum DCP_CURSOR2_UPDATE_LOCK {
2197 	DCP_CURSOR2_UPDATE_LOCK_FALSE                    = 0x0,
2198 	DCP_CURSOR2_UPDATE_LOCK_TRUE                     = 0x1,
2199 } DCP_CURSOR2_UPDATE_LOCK;
2200 typedef enum DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE {
2201 	DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_FALSE        = 0x0,
2202 	DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_TRUE         = 0x1,
2203 } DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE;
2204 typedef enum DCP_CURSOR2_UPDATE_STEREO_MODE {
2205 	DCP_CURSOR2_UPDATE_STEREO_MODE_BOTH              = 0x0,
2206 	DCP_CURSOR2_UPDATE_STEREO_MODE_SECONDARY_ONLY    = 0x1,
2207 	DCP_CURSOR2_UPDATE_STEREO_MODE_UNDEFINED         = 0x2,
2208 	DCP_CURSOR2_UPDATE_STEREO_MODE_PRIMARY_ONLY      = 0x3,
2209 } DCP_CURSOR2_UPDATE_STEREO_MODE;
2210 typedef enum DCP_CUR_REQUEST_FILTER_DIS {
2211 	DCP_CUR_REQUEST_FILTER_DIS_FALSE                 = 0x0,
2212 	DCP_CUR_REQUEST_FILTER_DIS_TRUE                  = 0x1,
2213 } DCP_CUR_REQUEST_FILTER_DIS;
2214 typedef enum DCP_CURSOR_STEREO_EN {
2215 	DCP_CURSOR_STEREO_EN_FALSE                       = 0x0,
2216 	DCP_CURSOR_STEREO_EN_TRUE                        = 0x1,
2217 } DCP_CURSOR_STEREO_EN;
2218 typedef enum DCP_CURSOR_STEREO_OFFSET_YNX {
2219 	DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION          = 0x0,
2220 	DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION          = 0x1,
2221 } DCP_CURSOR_STEREO_OFFSET_YNX;
2222 typedef enum DCP_CURSOR2_STEREO_EN {
2223 	DCP_CURSOR2_STEREO_EN_FALSE                      = 0x0,
2224 	DCP_CURSOR2_STEREO_EN_TRUE                       = 0x1,
2225 } DCP_CURSOR2_STEREO_EN;
2226 typedef enum DCP_CURSOR2_STEREO_OFFSET_YNX {
2227 	DCP_CURSOR2_STEREO_OFFSET_YNX_X_POSITION         = 0x0,
2228 	DCP_CURSOR2_STEREO_OFFSET_YNX_Y_POSITION         = 0x1,
2229 } DCP_CURSOR2_STEREO_OFFSET_YNX;
2230 typedef enum DCP_DC_LUT_RW_MODE {
2231 	DCP_DC_LUT_RW_MODE_256_ENTRY                     = 0x0,
2232 	DCP_DC_LUT_RW_MODE_PWL                           = 0x1,
2233 } DCP_DC_LUT_RW_MODE;
2234 typedef enum DCP_DC_LUT_VGA_ACCESS_ENABLE {
2235 	DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE               = 0x0,
2236 	DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE                = 0x1,
2237 } DCP_DC_LUT_VGA_ACCESS_ENABLE;
2238 typedef enum DCP_DC_LUT_AUTOFILL {
2239 	DCP_DC_LUT_AUTOFILL_FALSE                        = 0x0,
2240 	DCP_DC_LUT_AUTOFILL_TRUE                         = 0x1,
2241 } DCP_DC_LUT_AUTOFILL;
2242 typedef enum DCP_DC_LUT_AUTOFILL_DONE {
2243 	DCP_DC_LUT_AUTOFILL_DONE_FALSE                   = 0x0,
2244 	DCP_DC_LUT_AUTOFILL_DONE_TRUE                    = 0x1,
2245 } DCP_DC_LUT_AUTOFILL_DONE;
2246 typedef enum DCP_DC_LUT_INC_B {
2247 	DCP_DC_LUT_INC_B_NA                              = 0x0,
2248 	DCP_DC_LUT_INC_B_2                               = 0x1,
2249 	DCP_DC_LUT_INC_B_4                               = 0x2,
2250 	DCP_DC_LUT_INC_B_8                               = 0x3,
2251 	DCP_DC_LUT_INC_B_16                              = 0x4,
2252 	DCP_DC_LUT_INC_B_32                              = 0x5,
2253 	DCP_DC_LUT_INC_B_64                              = 0x6,
2254 	DCP_DC_LUT_INC_B_128                             = 0x7,
2255 	DCP_DC_LUT_INC_B_256                             = 0x8,
2256 	DCP_DC_LUT_INC_B_512                             = 0x9,
2257 } DCP_DC_LUT_INC_B;
2258 typedef enum DCP_DC_LUT_DATA_B_SIGNED_EN {
2259 	DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE                = 0x0,
2260 	DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE                 = 0x1,
2261 } DCP_DC_LUT_DATA_B_SIGNED_EN;
2262 typedef enum DCP_DC_LUT_DATA_B_FLOAT_POINT_EN {
2263 	DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE           = 0x0,
2264 	DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE            = 0x1,
2265 } DCP_DC_LUT_DATA_B_FLOAT_POINT_EN;
2266 typedef enum DCP_DC_LUT_DATA_B_FORMAT {
2267 	DCP_DC_LUT_DATA_B_FORMAT_U0P10                   = 0x0,
2268 	DCP_DC_LUT_DATA_B_FORMAT_S1P10                   = 0x1,
2269 	DCP_DC_LUT_DATA_B_FORMAT_U1P11                   = 0x2,
2270 	DCP_DC_LUT_DATA_B_FORMAT_U0P12                   = 0x3,
2271 } DCP_DC_LUT_DATA_B_FORMAT;
2272 typedef enum DCP_DC_LUT_INC_G {
2273 	DCP_DC_LUT_INC_G_NA                              = 0x0,
2274 	DCP_DC_LUT_INC_G_2                               = 0x1,
2275 	DCP_DC_LUT_INC_G_4                               = 0x2,
2276 	DCP_DC_LUT_INC_G_8                               = 0x3,
2277 	DCP_DC_LUT_INC_G_16                              = 0x4,
2278 	DCP_DC_LUT_INC_G_32                              = 0x5,
2279 	DCP_DC_LUT_INC_G_64                              = 0x6,
2280 	DCP_DC_LUT_INC_G_128                             = 0x7,
2281 	DCP_DC_LUT_INC_G_256                             = 0x8,
2282 	DCP_DC_LUT_INC_G_512                             = 0x9,
2283 } DCP_DC_LUT_INC_G;
2284 typedef enum DCP_DC_LUT_DATA_G_SIGNED_EN {
2285 	DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE                = 0x0,
2286 	DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE                 = 0x1,
2287 } DCP_DC_LUT_DATA_G_SIGNED_EN;
2288 typedef enum DCP_DC_LUT_DATA_G_FLOAT_POINT_EN {
2289 	DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE           = 0x0,
2290 	DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE            = 0x1,
2291 } DCP_DC_LUT_DATA_G_FLOAT_POINT_EN;
2292 typedef enum DCP_DC_LUT_DATA_G_FORMAT {
2293 	DCP_DC_LUT_DATA_G_FORMAT_U0P10                   = 0x0,
2294 	DCP_DC_LUT_DATA_G_FORMAT_S1P10                   = 0x1,
2295 	DCP_DC_LUT_DATA_G_FORMAT_U1P11                   = 0x2,
2296 	DCP_DC_LUT_DATA_G_FORMAT_U0P12                   = 0x3,
2297 } DCP_DC_LUT_DATA_G_FORMAT;
2298 typedef enum DCP_DC_LUT_INC_R {
2299 	DCP_DC_LUT_INC_R_NA                              = 0x0,
2300 	DCP_DC_LUT_INC_R_2                               = 0x1,
2301 	DCP_DC_LUT_INC_R_4                               = 0x2,
2302 	DCP_DC_LUT_INC_R_8                               = 0x3,
2303 	DCP_DC_LUT_INC_R_16                              = 0x4,
2304 	DCP_DC_LUT_INC_R_32                              = 0x5,
2305 	DCP_DC_LUT_INC_R_64                              = 0x6,
2306 	DCP_DC_LUT_INC_R_128                             = 0x7,
2307 	DCP_DC_LUT_INC_R_256                             = 0x8,
2308 	DCP_DC_LUT_INC_R_512                             = 0x9,
2309 } DCP_DC_LUT_INC_R;
2310 typedef enum DCP_DC_LUT_DATA_R_SIGNED_EN {
2311 	DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE                = 0x0,
2312 	DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE                 = 0x1,
2313 } DCP_DC_LUT_DATA_R_SIGNED_EN;
2314 typedef enum DCP_DC_LUT_DATA_R_FLOAT_POINT_EN {
2315 	DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE           = 0x0,
2316 	DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE            = 0x1,
2317 } DCP_DC_LUT_DATA_R_FLOAT_POINT_EN;
2318 typedef enum DCP_DC_LUT_DATA_R_FORMAT {
2319 	DCP_DC_LUT_DATA_R_FORMAT_U0P10                   = 0x0,
2320 	DCP_DC_LUT_DATA_R_FORMAT_S1P10                   = 0x1,
2321 	DCP_DC_LUT_DATA_R_FORMAT_U1P11                   = 0x2,
2322 	DCP_DC_LUT_DATA_R_FORMAT_U0P12                   = 0x3,
2323 } DCP_DC_LUT_DATA_R_FORMAT;
2324 typedef enum DCP_CRC_ENABLE {
2325 	DCP_CRC_ENABLE_FALSE                             = 0x0,
2326 	DCP_CRC_ENABLE_TRUE                              = 0x1,
2327 } DCP_CRC_ENABLE;
2328 typedef enum DCP_CRC_SOURCE_SEL {
2329 	DCP_CRC_SOURCE_SEL_OUTPUT_PIX                    = 0x0,
2330 	DCP_CRC_SOURCE_SEL_INPUT_L32                     = 0x1,
2331 	DCP_CRC_SOURCE_SEL_INPUT_H32                     = 0x2,
2332 	DCP_CRC_SOURCE_SEL_OUTPUT_CNTL                   = 0x4,
2333 } DCP_CRC_SOURCE_SEL;
2334 typedef enum DCP_CRC_LINE_SEL {
2335 	DCP_CRC_LINE_SEL_RESERVED                        = 0x0,
2336 	DCP_CRC_LINE_SEL_EVEN                            = 0x1,
2337 	DCP_CRC_LINE_SEL_ODD                             = 0x2,
2338 	DCP_CRC_LINE_SEL_BOTH                            = 0x3,
2339 } DCP_CRC_LINE_SEL;
2340 typedef enum DCP_GRPH_FLIP_RATE {
2341 	DCP_GRPH_FLIP_RATE_1FRAME                        = 0x0,
2342 	DCP_GRPH_FLIP_RATE_2FRAME                        = 0x1,
2343 	DCP_GRPH_FLIP_RATE_3FRAME                        = 0x2,
2344 	DCP_GRPH_FLIP_RATE_4FRAME                        = 0x3,
2345 	DCP_GRPH_FLIP_RATE_5FRAME                        = 0x4,
2346 	DCP_GRPH_FLIP_RATE_6FRAME                        = 0x5,
2347 	DCP_GRPH_FLIP_RATE_7FRAME                        = 0x6,
2348 	DCP_GRPH_FLIP_RATE_8FRAME                        = 0x7,
2349 } DCP_GRPH_FLIP_RATE;
2350 typedef enum DCP_GRPH_FLIP_RATE_ENABLE {
2351 	DCP_GRPH_FLIP_RATE_ENABLE_FALSE                  = 0x0,
2352 	DCP_GRPH_FLIP_RATE_ENABLE_TRUE                   = 0x1,
2353 } DCP_GRPH_FLIP_RATE_ENABLE;
2354 typedef enum DCP_GSL0_EN {
2355 	DCP_GSL0_EN_FALSE                                = 0x0,
2356 	DCP_GSL0_EN_TRUE                                 = 0x1,
2357 } DCP_GSL0_EN;
2358 typedef enum DCP_GSL1_EN {
2359 	DCP_GSL1_EN_FALSE                                = 0x0,
2360 	DCP_GSL1_EN_TRUE                                 = 0x1,
2361 } DCP_GSL1_EN;
2362 typedef enum DCP_GSL2_EN {
2363 	DCP_GSL2_EN_FALSE                                = 0x0,
2364 	DCP_GSL2_EN_TRUE                                 = 0x1,
2365 } DCP_GSL2_EN;
2366 typedef enum DCP_GSL_MASTER_EN {
2367 	DCP_GSL_MASTER_EN_FALSE                          = 0x0,
2368 	DCP_GSL_MASTER_EN_TRUE                           = 0x1,
2369 } DCP_GSL_MASTER_EN;
2370 typedef enum DCP_GSL_XDMA_GROUP {
2371 	DCP_GSL_XDMA_GROUP_VSYNC                         = 0x0,
2372 	DCP_GSL_XDMA_GROUP_HSYNC0                        = 0x1,
2373 	DCP_GSL_XDMA_GROUP_HSYNC1                        = 0x2,
2374 	DCP_GSL_XDMA_GROUP_HSYNC2                        = 0x3,
2375 } DCP_GSL_XDMA_GROUP;
2376 typedef enum DCP_GSL_XDMA_GROUP_UNDERFLOW_EN {
2377 	DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE            = 0x0,
2378 	DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE             = 0x1,
2379 } DCP_GSL_XDMA_GROUP_UNDERFLOW_EN;
2380 typedef enum DCP_GSL_SYNC_SOURCE {
2381 	DCP_GSL_SYNC_SOURCE_FLIP                         = 0x0,
2382 	DCP_GSL_SYNC_SOURCE_PHASE0                       = 0x1,
2383 	DCP_GSL_SYNC_SOURCE_RESET                        = 0x2,
2384 	DCP_GSL_SYNC_SOURCE_PHASE1                       = 0x3,
2385 } DCP_GSL_SYNC_SOURCE;
2386 typedef enum DCP_GSL_DELAY_SURFACE_UPDATE_PENDING {
2387 	DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE       = 0x0,
2388 	DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE        = 0x1,
2389 } DCP_GSL_DELAY_SURFACE_UPDATE_PENDING;
2390 typedef enum DCP_TEST_DEBUG_WRITE_EN {
2391 	DCP_TEST_DEBUG_WRITE_EN_FALSE                    = 0x0,
2392 	DCP_TEST_DEBUG_WRITE_EN_TRUE                     = 0x1,
2393 } DCP_TEST_DEBUG_WRITE_EN;
2394 typedef enum DCP_GRPH_STEREOSYNC_FLIP_EN {
2395 	DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE                = 0x0,
2396 	DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE                 = 0x1,
2397 } DCP_GRPH_STEREOSYNC_FLIP_EN;
2398 typedef enum DCP_GRPH_STEREOSYNC_FLIP_MODE {
2399 	DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP               = 0x0,
2400 	DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0             = 0x1,
2401 	DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET              = 0x2,
2402 	DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1             = 0x3,
2403 } DCP_GRPH_STEREOSYNC_FLIP_MODE;
2404 typedef enum DCP_GRPH_STEREOSYNC_SELECT_DISABLE {
2405 	DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE         = 0x0,
2406 	DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE          = 0x1,
2407 } DCP_GRPH_STEREOSYNC_SELECT_DISABLE;
2408 typedef enum DCP_GRPH_ROTATION_ANGLE {
2409 	DCP_GRPH_ROTATION_ANGLE_0                        = 0x0,
2410 	DCP_GRPH_ROTATION_ANGLE_90                       = 0x1,
2411 	DCP_GRPH_ROTATION_ANGLE_180                      = 0x2,
2412 	DCP_GRPH_ROTATION_ANGLE_270                      = 0x3,
2413 } DCP_GRPH_ROTATION_ANGLE;
2414 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN {
2415 	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE       = 0x0,
2416 	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE        = 0x1,
2417 } DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN;
2418 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE {
2419 	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM  = 0x0,
2420 	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE= 0x1,
2421 } DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE;
2422 typedef enum DCP_GRPH_REGAMMA_MODE {
2423 	DCP_GRPH_REGAMMA_MODE_BYPASS                     = 0x0,
2424 	DCP_GRPH_REGAMMA_MODE_SRGB                       = 0x1,
2425 	DCP_GRPH_REGAMMA_MODE_XVYCC                      = 0x2,
2426 	DCP_GRPH_REGAMMA_MODE_PROGA                      = 0x3,
2427 	DCP_GRPH_REGAMMA_MODE_PROGB                      = 0x4,
2428 } DCP_GRPH_REGAMMA_MODE;
2429 typedef enum DCP_ALPHA_ROUND_TRUNC_MODE {
2430 	DCP_ALPHA_ROUND_TRUNC_MODE_ROUND                 = 0x0,
2431 	DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC                 = 0x1,
2432 } DCP_ALPHA_ROUND_TRUNC_MODE;
2433 typedef enum DCP_CURSOR_ALPHA_BLND_ENA {
2434 	DCP_CURSOR_ALPHA_BLND_ENA_FALSE                  = 0x0,
2435 	DCP_CURSOR_ALPHA_BLND_ENA_TRUE                   = 0x1,
2436 } DCP_CURSOR_ALPHA_BLND_ENA;
2437 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK {
2438 	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE   = 0x0,
2439 	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE    = 0x1,
2440 } DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK;
2441 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK {
2442 	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE    = 0x0,
2443 	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE     = 0x1,
2444 } DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK;
2445 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK {
2446 	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE     = 0x0,
2447 	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE      = 0x1,
2448 } DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK;
2449 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK {
2450 	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE      = 0x0,
2451 	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE       = 0x1,
2452 } DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK;
2453 typedef enum DCP_GRPH_SURFACE_COUNTER_EN {
2454 	DCP_GRPH_SURFACE_COUNTER_EN_DISABLE              = 0x0,
2455 	DCP_GRPH_SURFACE_COUNTER_EN_ENABLE               = 0x1,
2456 } DCP_GRPH_SURFACE_COUNTER_EN;
2457 typedef enum DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT {
2458 	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0          = 0x0,
2459 	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1          = 0x1,
2460 	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2          = 0x2,
2461 	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3          = 0x3,
2462 	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4          = 0x4,
2463 	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5          = 0x5,
2464 	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6          = 0x6,
2465 	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7          = 0x7,
2466 	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8          = 0x8,
2467 	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9          = 0x9,
2468 	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10         = 0xa,
2469 	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11         = 0xb,
2470 } DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT;
2471 typedef enum DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED {
2472 	DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO     = 0x0,
2473 	DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES    = 0x1,
2474 } DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED;
2475 typedef enum HDMI_KEEPOUT_MODE {
2476 	HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC                = 0x0,
2477 	HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC              = 0x1,
2478 } HDMI_KEEPOUT_MODE;
2479 typedef enum HDMI_CLOCK_CHANNEL_RATE {
2480 	HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE       = 0x0,
2481 	HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE     = 0x1,
2482 } HDMI_CLOCK_CHANNEL_RATE;
2483 typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
2484 	HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE             = 0x0,
2485 	HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE            = 0x1,
2486 } HDMI_NO_EXTRA_NULL_PACKET_FILLED;
2487 typedef enum HDMI_PACKET_GEN_VERSION {
2488 	HDMI_PACKET_GEN_VERSION_OLD                      = 0x0,
2489 	HDMI_PACKET_GEN_VERSION_NEW                      = 0x1,
2490 } HDMI_PACKET_GEN_VERSION;
2491 typedef enum HDMI_ERROR_ACK {
2492 	HDMI_ERROR_ACK_INT                               = 0x0,
2493 	HDMI_ERROR_NOT_ACK                               = 0x1,
2494 } HDMI_ERROR_ACK;
2495 typedef enum HDMI_ERROR_MASK {
2496 	HDMI_ERROR_MASK_INT                              = 0x0,
2497 	HDMI_ERROR_NOT_MASK                              = 0x1,
2498 } HDMI_ERROR_MASK;
2499 typedef enum HDMI_DEEP_COLOR_DEPTH {
2500 	HDMI_DEEP_COLOR_DEPTH_24BPP                      = 0x0,
2501 	HDMI_DEEP_COLOR_DEPTH_30BPP                      = 0x1,
2502 	HDMI_DEEP_COLOR_DEPTH_36BPP                      = 0x2,
2503 	HDMI_DEEP_COLOR_DEPTH_RESERVED                   = 0x3,
2504 } HDMI_DEEP_COLOR_DEPTH;
2505 typedef enum HDMI_AUDIO_DELAY_EN {
2506 	HDMI_AUDIO_DELAY_DISABLE                         = 0x0,
2507 	HDMI_AUDIO_DELAY_58CLK                           = 0x1,
2508 	HDMI_AUDIO_DELAY_56CLK                           = 0x2,
2509 	HDMI_AUDIO_DELAY_RESERVED                        = 0x3,
2510 } HDMI_AUDIO_DELAY_EN;
2511 typedef enum HDMI_AUDIO_SEND_MAX_PACKETS {
2512 	HDMI_NOT_SEND_MAX_AUDIO_PACKETS                  = 0x0,
2513 	HDMI_SEND_MAX_AUDIO_PACKETS                      = 0x1,
2514 } HDMI_AUDIO_SEND_MAX_PACKETS;
2515 typedef enum HDMI_ACR_SEND {
2516 	HDMI_ACR_NOT_SEND                                = 0x0,
2517 	HDMI_ACR_PKT_SEND                                = 0x1,
2518 } HDMI_ACR_SEND;
2519 typedef enum HDMI_ACR_CONT {
2520 	HDMI_ACR_CONT_DISABLE                            = 0x0,
2521 	HDMI_ACR_CONT_ENABLE                             = 0x1,
2522 } HDMI_ACR_CONT;
2523 typedef enum HDMI_ACR_SELECT {
2524 	HDMI_ACR_SELECT_HW                               = 0x0,
2525 	HDMI_ACR_SELECT_32K                              = 0x1,
2526 	HDMI_ACR_SELECT_44K                              = 0x2,
2527 	HDMI_ACR_SELECT_48K                              = 0x3,
2528 } HDMI_ACR_SELECT;
2529 typedef enum HDMI_ACR_SOURCE {
2530 	HDMI_ACR_SOURCE_HW                               = 0x0,
2531 	HDMI_ACR_SOURCE_SW                               = 0x1,
2532 } HDMI_ACR_SOURCE;
2533 typedef enum HDMI_ACR_N_MULTIPLE {
2534 	HDMI_ACR_0_MULTIPLE_RESERVED                     = 0x0,
2535 	HDMI_ACR_1_MULTIPLE                              = 0x1,
2536 	HDMI_ACR_2_MULTIPLE                              = 0x2,
2537 	HDMI_ACR_3_MULTIPLE_RESERVED                     = 0x3,
2538 	HDMI_ACR_4_MULTIPLE                              = 0x4,
2539 	HDMI_ACR_5_MULTIPLE_RESERVED                     = 0x5,
2540 	HDMI_ACR_6_MULTIPLE_RESERVED                     = 0x6,
2541 	HDMI_ACR_7_MULTIPLE_RESERVED                     = 0x7,
2542 } HDMI_ACR_N_MULTIPLE;
2543 typedef enum HDMI_ACR_AUDIO_PRIORITY {
2544 	HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE     = 0x0,
2545 	HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT     = 0x1,
2546 } HDMI_ACR_AUDIO_PRIORITY;
2547 typedef enum HDMI_NULL_SEND {
2548 	HDMI_NULL_NOT_SEND                               = 0x0,
2549 	HDMI_NULL_PKT_SEND                               = 0x1,
2550 } HDMI_NULL_SEND;
2551 typedef enum HDMI_GC_SEND {
2552 	HDMI_GC_NOT_SEND                                 = 0x0,
2553 	HDMI_GC_PKT_SEND                                 = 0x1,
2554 } HDMI_GC_SEND;
2555 typedef enum HDMI_GC_CONT {
2556 	HDMI_GC_CONT_DISABLE                             = 0x0,
2557 	HDMI_GC_CONT_ENABLE                              = 0x1,
2558 } HDMI_GC_CONT;
2559 typedef enum HDMI_ISRC_SEND {
2560 	HDMI_ISRC_NOT_SEND                               = 0x0,
2561 	HDMI_ISRC_PKT_SEND                               = 0x1,
2562 } HDMI_ISRC_SEND;
2563 typedef enum HDMI_ISRC_CONT {
2564 	HDMI_ISRC_CONT_DISABLE                           = 0x0,
2565 	HDMI_ISRC_CONT_ENABLE                            = 0x1,
2566 } HDMI_ISRC_CONT;
2567 typedef enum HDMI_AVI_INFO_SEND {
2568 	HDMI_AVI_INFO_NOT_SEND                           = 0x0,
2569 	HDMI_AVI_INFO_PKT_SEND                           = 0x1,
2570 } HDMI_AVI_INFO_SEND;
2571 typedef enum HDMI_AVI_INFO_CONT {
2572 	HDMI_AVI_INFO_CONT_DISABLE                       = 0x0,
2573 	HDMI_AVI_INFO_CONT_ENABLE                        = 0x1,
2574 } HDMI_AVI_INFO_CONT;
2575 typedef enum HDMI_AUDIO_INFO_SEND {
2576 	HDMI_AUDIO_INFO_NOT_SEND                         = 0x0,
2577 	HDMI_AUDIO_INFO_PKT_SEND                         = 0x1,
2578 } HDMI_AUDIO_INFO_SEND;
2579 typedef enum HDMI_AUDIO_INFO_CONT {
2580 	HDMI_AUDIO_INFO_CONT_DISABLE                     = 0x0,
2581 	HDMI_AUDIO_INFO_CONT_ENABLE                      = 0x1,
2582 } HDMI_AUDIO_INFO_CONT;
2583 typedef enum HDMI_MPEG_INFO_SEND {
2584 	HDMI_MPEG_INFO_NOT_SEND                          = 0x0,
2585 	HDMI_MPEG_INFO_PKT_SEND                          = 0x1,
2586 } HDMI_MPEG_INFO_SEND;
2587 typedef enum HDMI_MPEG_INFO_CONT {
2588 	HDMI_MPEG_INFO_CONT_DISABLE                      = 0x0,
2589 	HDMI_MPEG_INFO_CONT_ENABLE                       = 0x1,
2590 } HDMI_MPEG_INFO_CONT;
2591 typedef enum HDMI_GENERIC0_SEND {
2592 	HDMI_GENERIC0_NOT_SEND                           = 0x0,
2593 	HDMI_GENERIC0_PKT_SEND                           = 0x1,
2594 } HDMI_GENERIC0_SEND;
2595 typedef enum HDMI_GENERIC0_CONT {
2596 	HDMI_GENERIC0_CONT_DISABLE                       = 0x0,
2597 	HDMI_GENERIC0_CONT_ENABLE                        = 0x1,
2598 } HDMI_GENERIC0_CONT;
2599 typedef enum HDMI_GENERIC1_SEND {
2600 	HDMI_GENERIC1_NOT_SEND                           = 0x0,
2601 	HDMI_GENERIC1_PKT_SEND                           = 0x1,
2602 } HDMI_GENERIC1_SEND;
2603 typedef enum HDMI_GENERIC1_CONT {
2604 	HDMI_GENERIC1_CONT_DISABLE                       = 0x0,
2605 	HDMI_GENERIC1_CONT_ENABLE                        = 0x1,
2606 } HDMI_GENERIC1_CONT;
2607 typedef enum HDMI_GC_AVMUTE_CONT {
2608 	HDMI_GC_AVMUTE_CONT_DISABLE                      = 0x0,
2609 	HDMI_GC_AVMUTE_CONT_ENABLE                       = 0x1,
2610 } HDMI_GC_AVMUTE_CONT;
2611 typedef enum HDMI_PACKING_PHASE_OVERRIDE {
2612 	HDMI_PACKING_PHASE_SET_BY_HW                     = 0x0,
2613 	HDMI_PACKING_PHASE_SET_BY_SW                     = 0x1,
2614 } HDMI_PACKING_PHASE_OVERRIDE;
2615 typedef enum HDMI_GENERIC2_SEND {
2616 	HDMI_GENERIC2_NOT_SEND                           = 0x0,
2617 	HDMI_GENERIC2_PKT_SEND                           = 0x1,
2618 } HDMI_GENERIC2_SEND;
2619 typedef enum HDMI_GENERIC2_CONT {
2620 	HDMI_GENERIC2_CONT_DISABLE                       = 0x0,
2621 	HDMI_GENERIC2_CONT_ENABLE                        = 0x1,
2622 } HDMI_GENERIC2_CONT;
2623 typedef enum HDMI_GENERIC3_SEND {
2624 	HDMI_GENERIC3_NOT_SEND                           = 0x0,
2625 	HDMI_GENERIC3_PKT_SEND                           = 0x1,
2626 } HDMI_GENERIC3_SEND;
2627 typedef enum HDMI_GENERIC3_CONT {
2628 	HDMI_GENERIC3_CONT_DISABLE                       = 0x0,
2629 	HDMI_GENERIC3_CONT_ENABLE                        = 0x1,
2630 } HDMI_GENERIC3_CONT;
2631 typedef enum TMDS_PIXEL_ENCODING {
2632 	TMDS_PIXEL_ENCODING_444_OR_420                   = 0x0,
2633 	TMDS_PIXEL_ENCODING_422                          = 0x1,
2634 } TMDS_PIXEL_ENCODING;
2635 typedef enum TMDS_COLOR_FORMAT {
2636 	TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP= 0x0,
2637 	TMDS_COLOR_FORMAT_TWIN30BPP_LSB                  = 0x1,
2638 	TMDS_COLOR_FORMAT_DUAL30BPP                      = 0x2,
2639 	TMDS_COLOR_FORMAT_RESERVED                       = 0x3,
2640 } TMDS_COLOR_FORMAT;
2641 typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
2642 	TMDS_STEREOSYNC_CTL0                             = 0x0,
2643 	TMDS_STEREOSYNC_CTL1                             = 0x1,
2644 	TMDS_STEREOSYNC_CTL2                             = 0x2,
2645 	TMDS_STEREOSYNC_CTL3                             = 0x3,
2646 } TMDS_STEREOSYNC_CTL_SEL_REG;
2647 typedef enum TMDS_CTL0_DATA_SEL {
2648 	TMDS_CTL0_DATA_SEL0_RESERVED                     = 0x0,
2649 	TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE               = 0x1,
2650 	TMDS_CTL0_DATA_SEL2_VSYNC                        = 0x2,
2651 	TMDS_CTL0_DATA_SEL3_RESERVED                     = 0x3,
2652 	TMDS_CTL0_DATA_SEL4_HSYNC                        = 0x4,
2653 	TMDS_CTL0_DATA_SEL5_SEL7_RESERVED                = 0x5,
2654 	TMDS_CTL0_DATA_SEL8_RANDOM_DATA                  = 0x6,
2655 	TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA            = 0x7,
2656 } TMDS_CTL0_DATA_SEL;
2657 typedef enum TMDS_CTL0_DATA_INVERT {
2658 	TMDS_CTL0_DATA_NORMAL                            = 0x0,
2659 	TMDS_CTL0_DATA_INVERT_EN                         = 0x1,
2660 } TMDS_CTL0_DATA_INVERT;
2661 typedef enum TMDS_CTL0_DATA_MODULATION {
2662 	TMDS_CTL0_DATA_MODULATION_DISABLE                = 0x0,
2663 	TMDS_CTL0_DATA_MODULATION_BIT0                   = 0x1,
2664 	TMDS_CTL0_DATA_MODULATION_BIT1                   = 0x2,
2665 	TMDS_CTL0_DATA_MODULATION_BIT2                   = 0x3,
2666 } TMDS_CTL0_DATA_MODULATION;
2667 typedef enum TMDS_CTL0_PATTERN_OUT_EN {
2668 	TMDS_CTL0_PATTERN_OUT_DISABLE                    = 0x0,
2669 	TMDS_CTL0_PATTERN_OUT_ENABLE                     = 0x1,
2670 } TMDS_CTL0_PATTERN_OUT_EN;
2671 typedef enum TMDS_CTL1_DATA_SEL {
2672 	TMDS_CTL1_DATA_SEL0_RESERVED                     = 0x0,
2673 	TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE               = 0x1,
2674 	TMDS_CTL1_DATA_SEL2_VSYNC                        = 0x2,
2675 	TMDS_CTL1_DATA_SEL3_RESERVED                     = 0x3,
2676 	TMDS_CTL1_DATA_SEL4_HSYNC                        = 0x4,
2677 	TMDS_CTL1_DATA_SEL5_SEL7_RESERVED                = 0x5,
2678 	TMDS_CTL1_DATA_SEL8_BLANK_TIME                   = 0x6,
2679 	TMDS_CTL1_DATA_SEL9_SEL15_RESERVED               = 0x7,
2680 } TMDS_CTL1_DATA_SEL;
2681 typedef enum TMDS_CTL1_DATA_INVERT {
2682 	TMDS_CTL1_DATA_NORMAL                            = 0x0,
2683 	TMDS_CTL1_DATA_INVERT_EN                         = 0x1,
2684 } TMDS_CTL1_DATA_INVERT;
2685 typedef enum TMDS_CTL1_DATA_MODULATION {
2686 	TMDS_CTL1_DATA_MODULATION_DISABLE                = 0x0,
2687 	TMDS_CTL1_DATA_MODULATION_BIT0                   = 0x1,
2688 	TMDS_CTL1_DATA_MODULATION_BIT1                   = 0x2,
2689 	TMDS_CTL1_DATA_MODULATION_BIT2                   = 0x3,
2690 } TMDS_CTL1_DATA_MODULATION;
2691 typedef enum TMDS_CTL1_PATTERN_OUT_EN {
2692 	TMDS_CTL1_PATTERN_OUT_DISABLE                    = 0x0,
2693 	TMDS_CTL1_PATTERN_OUT_ENABLE                     = 0x1,
2694 } TMDS_CTL1_PATTERN_OUT_EN;
2695 typedef enum TMDS_CTL2_DATA_SEL {
2696 	TMDS_CTL2_DATA_SEL0_RESERVED                     = 0x0,
2697 	TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE               = 0x1,
2698 	TMDS_CTL2_DATA_SEL2_VSYNC                        = 0x2,
2699 	TMDS_CTL2_DATA_SEL3_RESERVED                     = 0x3,
2700 	TMDS_CTL2_DATA_SEL4_HSYNC                        = 0x4,
2701 	TMDS_CTL2_DATA_SEL5_SEL7_RESERVED                = 0x5,
2702 	TMDS_CTL2_DATA_SEL8_BLANK_TIME                   = 0x6,
2703 	TMDS_CTL2_DATA_SEL9_SEL15_RESERVED               = 0x7,
2704 } TMDS_CTL2_DATA_SEL;
2705 typedef enum TMDS_CTL2_DATA_INVERT {
2706 	TMDS_CTL2_DATA_NORMAL                            = 0x0,
2707 	TMDS_CTL2_DATA_INVERT_EN                         = 0x1,
2708 } TMDS_CTL2_DATA_INVERT;
2709 typedef enum TMDS_CTL2_DATA_MODULATION {
2710 	TMDS_CTL2_DATA_MODULATION_DISABLE                = 0x0,
2711 	TMDS_CTL2_DATA_MODULATION_BIT0                   = 0x1,
2712 	TMDS_CTL2_DATA_MODULATION_BIT1                   = 0x2,
2713 	TMDS_CTL2_DATA_MODULATION_BIT2                   = 0x3,
2714 } TMDS_CTL2_DATA_MODULATION;
2715 typedef enum TMDS_CTL2_PATTERN_OUT_EN {
2716 	TMDS_CTL2_PATTERN_OUT_DISABLE                    = 0x0,
2717 	TMDS_CTL2_PATTERN_OUT_ENABLE                     = 0x1,
2718 } TMDS_CTL2_PATTERN_OUT_EN;
2719 typedef enum TMDS_CTL3_DATA_INVERT {
2720 	TMDS_CTL3_DATA_NORMAL                            = 0x0,
2721 	TMDS_CTL3_DATA_INVERT_EN                         = 0x1,
2722 } TMDS_CTL3_DATA_INVERT;
2723 typedef enum TMDS_CTL3_DATA_MODULATION {
2724 	TMDS_CTL3_DATA_MODULATION_DISABLE                = 0x0,
2725 	TMDS_CTL3_DATA_MODULATION_BIT0                   = 0x1,
2726 	TMDS_CTL3_DATA_MODULATION_BIT1                   = 0x2,
2727 	TMDS_CTL3_DATA_MODULATION_BIT2                   = 0x3,
2728 } TMDS_CTL3_DATA_MODULATION;
2729 typedef enum TMDS_CTL3_PATTERN_OUT_EN {
2730 	TMDS_CTL3_PATTERN_OUT_DISABLE                    = 0x0,
2731 	TMDS_CTL3_PATTERN_OUT_ENABLE                     = 0x1,
2732 } TMDS_CTL3_PATTERN_OUT_EN;
2733 typedef enum TMDS_CTL3_DATA_SEL {
2734 	TMDS_CTL3_DATA_SEL0_RESERVED                     = 0x0,
2735 	TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE               = 0x1,
2736 	TMDS_CTL3_DATA_SEL2_VSYNC                        = 0x2,
2737 	TMDS_CTL3_DATA_SEL3_RESERVED                     = 0x3,
2738 	TMDS_CTL3_DATA_SEL4_HSYNC                        = 0x4,
2739 	TMDS_CTL3_DATA_SEL5_SEL7_RESERVED                = 0x5,
2740 	TMDS_CTL3_DATA_SEL8_BLANK_TIME                   = 0x6,
2741 	TMDS_CTL3_DATA_SEL9_SEL15_RESERVED               = 0x7,
2742 } TMDS_CTL3_DATA_SEL;
2743 typedef enum DIG_FE_CNTL_SOURCE_SELECT {
2744 	DIG_FE_SOURCE_FROM_FMT0                          = 0x0,
2745 	DIG_FE_SOURCE_FROM_FMT1                          = 0x1,
2746 	DIG_FE_SOURCE_FROM_FMT2                          = 0x2,
2747 	DIG_FE_SOURCE_FROM_FMT3                          = 0x3,
2748 	DIG_FE_SOURCE_FROM_FMT4                          = 0x4,
2749 	DIG_FE_SOURCE_FROM_FMT5                          = 0x5,
2750 } DIG_FE_CNTL_SOURCE_SELECT;
2751 typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
2752 	DIG_FE_STEREOSYNC_FROM_FMT0                      = 0x0,
2753 	DIG_FE_STEREOSYNC_FROM_FMT1                      = 0x1,
2754 	DIG_FE_STEREOSYNC_FROM_FMT2                      = 0x2,
2755 	DIG_FE_STEREOSYNC_FROM_FMT3                      = 0x3,
2756 	DIG_FE_STEREOSYNC_FROM_FMT4                      = 0x4,
2757 	DIG_FE_STEREOSYNC_FROM_FMT5                      = 0x5,
2758 } DIG_FE_CNTL_STEREOSYNC_SELECT;
2759 typedef enum DIG_FIFO_READ_CLOCK_SRC {
2760 	DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG                = 0x0,
2761 	DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE        = 0x1,
2762 } DIG_FIFO_READ_CLOCK_SRC;
2763 typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
2764 	DIG_OUTPUT_CRC_ON_LINK0                          = 0x0,
2765 	DIG_OUTPUT_CRC_ON_LINK1                          = 0x1,
2766 } DIG_OUTPUT_CRC_CNTL_LINK_SEL;
2767 typedef enum DIG_OUTPUT_CRC_DATA_SEL {
2768 	DIG_OUTPUT_CRC_FOR_FULLFRAME                     = 0x0,
2769 	DIG_OUTPUT_CRC_FOR_ACTIVEONLY                    = 0x1,
2770 	DIG_OUTPUT_CRC_FOR_VBI                           = 0x2,
2771 	DIG_OUTPUT_CRC_FOR_AUDIO                         = 0x3,
2772 } DIG_OUTPUT_CRC_DATA_SEL;
2773 typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
2774 	DIG_IN_NORMAL_OPERATION                          = 0x0,
2775 	DIG_IN_DEBUG_MODE                                = 0x1,
2776 } DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN;
2777 typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
2778 	DIG_10BIT_TEST_PATTERN                           = 0x0,
2779 	DIG_ALTERNATING_TEST_PATTERN                     = 0x1,
2780 } DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL;
2781 typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
2782 	DIG_TEST_PATTERN_NORMAL                          = 0x0,
2783 	DIG_TEST_PATTERN_RANDOM                          = 0x1,
2784 } DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN;
2785 typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
2786 	DIG_RANDOM_PATTERN_ENABLED                       = 0x0,
2787 	DIG_RANDOM_PATTERN_RESETED                       = 0x1,
2788 } DIG_TEST_PATTERN_RANDOM_PATTERN_RESET;
2789 typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
2790 	DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE           = 0x0,
2791 	DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG       = 0x1,
2792 } DIG_TEST_PATTERN_EXTERNAL_RESET_EN;
2793 typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
2794 	DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS       = 0x0,
2795 	DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH          = 0x1,
2796 } DIG_RANDOM_PATTERN_SEED_RAN_PAT;
2797 typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL {
2798 	DIG_FIFO_USE_OVERWRITE_LEVEL                     = 0x0,
2799 	DIG_FIFO_USE_CAL_AVERAGE_LEVEL                   = 0x1,
2800 } DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL;
2801 typedef enum DIG_FIFO_ERROR_ACK {
2802 	DIG_FIFO_ERROR_ACK_INT                           = 0x0,
2803 	DIG_FIFO_ERROR_NOT_ACK                           = 0x1,
2804 } DIG_FIFO_ERROR_ACK;
2805 typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE {
2806 	DIG_FIFO_NOT_FORCE_RECAL_AVERAGE                 = 0x0,
2807 	DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL               = 0x1,
2808 } DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE;
2809 typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX {
2810 	DIG_FIFO_NOT_FORCE_RECOMP_MINMAX                 = 0x0,
2811 	DIG_FIFO_FORCE_RECOMP_MINMAX                     = 0x1,
2812 } DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX;
2813 typedef enum DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT {
2814 	DIG_DISPCLK_SWITCH_AT_EARLY_VBLANK               = 0x0,
2815 	DIG_DISPCLK_SWITCH_AT_FIRST_HSYNC                = 0x1,
2816 } DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT;
2817 typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK {
2818 	DIG_DISPCLK_SWITCH_ALLOWED_ACK_INT               = 0x0,
2819 	DIG_DISPCLK_SWITCH_ALLOWED_INT_NOT_ACK           = 0x1,
2820 } DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK;
2821 typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK {
2822 	DIG_DISPCLK_SWITCH_ALLOWED_MASK_INT              = 0x0,
2823 	DIG_DISPCLK_SWITCH_ALLOWED_INT_UNMASK            = 0x1,
2824 } DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK;
2825 typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
2826 	AFMT_INTERRUPT_DISABLE                           = 0x0,
2827 	AFMT_INTERRUPT_ENABLE                            = 0x1,
2828 } AFMT_INTERRUPT_STATUS_CHG_MASK;
2829 typedef enum HDMI_GC_AVMUTE {
2830 	HDMI_GC_AVMUTE_SET                               = 0x0,
2831 	HDMI_GC_AVMUTE_UNSET                             = 0x1,
2832 } HDMI_GC_AVMUTE;
2833 typedef enum HDMI_DEFAULT_PAHSE {
2834 	HDMI_DEFAULT_PHASE_IS_0                          = 0x0,
2835 	HDMI_DEFAULT_PHASE_IS_1                          = 0x1,
2836 } HDMI_DEFAULT_PAHSE;
2837 typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
2838 	AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS= 0x0,
2839 	AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER               = 0x1,
2840 } AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD;
2841 typedef enum AUDIO_LAYOUT_SELECT {
2842 	AUDIO_LAYOUT_0                                   = 0x0,
2843 	AUDIO_LAYOUT_1                                   = 0x1,
2844 } AUDIO_LAYOUT_SELECT;
2845 typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
2846 	AFMT_AUDIO_CRC_ONESHOT                           = 0x0,
2847 	AFMT_AUDIO_CRC_AUTO_RESTART                      = 0x1,
2848 } AFMT_AUDIO_CRC_CONTROL_CONT;
2849 typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
2850 	AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT            = 0x0,
2851 	AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT           = 0x1,
2852 } AFMT_AUDIO_CRC_CONTROL_SOURCE;
2853 typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
2854 	AFMT_AUDIO_CRC_CH0_SIG                           = 0x0,
2855 	AFMT_AUDIO_CRC_CH1_SIG                           = 0x1,
2856 	AFMT_AUDIO_CRC_CH2_SIG                           = 0x2,
2857 	AFMT_AUDIO_CRC_CH3_SIG                           = 0x3,
2858 	AFMT_AUDIO_CRC_CH4_SIG                           = 0x4,
2859 	AFMT_AUDIO_CRC_CH5_SIG                           = 0x5,
2860 	AFMT_AUDIO_CRC_CH6_SIG                           = 0x6,
2861 	AFMT_AUDIO_CRC_CH7_SIG                           = 0x7,
2862 	AFMT_AUDIO_CRC_RESERVED                          = 0x8,
2863 	AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT                = 0x9,
2864 } AFMT_AUDIO_CRC_CONTROL_CH_SEL;
2865 typedef enum AFMT_RAMP_CONTROL0_SIGN {
2866 	AFMT_RAMP_SIGNED                                 = 0x0,
2867 	AFMT_RAMP_UNSIGNED                               = 0x1,
2868 } AFMT_RAMP_CONTROL0_SIGN;
2869 typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
2870 	AFMT_AUDIO_PACKET_SENT_DISABLED                  = 0x0,
2871 	AFMT_AUDIO_PACKET_SENT_ENABLED                   = 0x1,
2872 } AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND;
2873 typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
2874 	AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED= 0x0,
2875 	AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED        = 0x1,
2876 } AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS;
2877 typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
2878 	AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK          = 0x0,
2879 	AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS        = 0x1,
2880 } AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE;
2881 typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
2882 	AFMT_AUDIO_SRC_FROM_AZ_STREAM0                   = 0x0,
2883 	AFMT_AUDIO_SRC_FROM_AZ_STREAM1                   = 0x1,
2884 	AFMT_AUDIO_SRC_FROM_AZ_STREAM2                   = 0x2,
2885 	AFMT_AUDIO_SRC_FROM_AZ_STREAM3                   = 0x3,
2886 	AFMT_AUDIO_SRC_FROM_AZ_STREAM4                   = 0x4,
2887 	AFMT_AUDIO_SRC_FROM_AZ_STREAM5                   = 0x5,
2888 	AFMT_AUDIO_SRC_RESERVED                          = 0x6,
2889 } AFMT_AUDIO_SRC_CONTROL_SELECT;
2890 typedef enum DIG_BE_CNTL_MODE {
2891 	DIG_BE_DP_SST_MODE                               = 0x0,
2892 	DIG_BE_RESERVED1                                 = 0x1,
2893 	DIG_BE_TMDS_DVI_MODE                             = 0x2,
2894 	DIG_BE_TMDS_HDMI_MODE                            = 0x3,
2895 	DIG_BE_SDVO_RESERVED                             = 0x4,
2896 	DIG_BE_DP_MST_MODE                               = 0x5,
2897 	DIG_BE_RESERVED2                                 = 0x6,
2898 	DIG_BE_RESERVED3                                 = 0x7,
2899 } DIG_BE_CNTL_MODE;
2900 typedef enum DIG_BE_CNTL_HPD_SELECT {
2901 	DIG_BE_CNTL_HPD1                                 = 0x0,
2902 	DIG_BE_CNTL_HPD2                                 = 0x1,
2903 	DIG_BE_CNTL_HPD3                                 = 0x2,
2904 	DIG_BE_CNTL_HPD4                                 = 0x3,
2905 	DIG_BE_CNTL_HPD5                                 = 0x4,
2906 	DIG_BE_CNTL_HPD6                                 = 0x5,
2907 } DIG_BE_CNTL_HPD_SELECT;
2908 typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
2909 	LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS             = 0x0,
2910 	LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH           = 0x1,
2911 } LVTMA_RANDOM_PATTERN_SEED_RAN_PAT;
2912 typedef enum TMDS_SYNC_PHASE {
2913 	TMDS_NOT_SYNC_PHASE_ON_FRAME_START               = 0x0,
2914 	TMDS_SYNC_PHASE_ON_FRAME_START                   = 0x1,
2915 } TMDS_SYNC_PHASE;
2916 typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
2917 	TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS     = 0x0,
2918 	TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL      = 0x1,
2919 } TMDS_DATA_SYNCHRONIZATION_DSINTSEL;
2920 typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
2921 	TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE           = 0x0,
2922 	TMDS_TRANSMITTER_HPD_MASK_OVERRIDE               = 0x1,
2923 } TMDS_TRANSMITTER_ENABLE_HPD_MASK;
2924 typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
2925 	TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE    = 0x0,
2926 	TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE        = 0x1,
2927 } TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK;
2928 typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
2929 	TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE    = 0x0,
2930 	TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE        = 0x1,
2931 } TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK;
2932 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
2933 	TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE     = 0x0,
2934 	TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON= 0x1,
2935 	TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON  = 0x2,
2936 	TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE         = 0x3,
2937 } TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK;
2938 typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
2939 	TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK           = 0x0,
2940 	TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK             = 0x1,
2941 } TMDS_TRANSMITTER_CONTROL_IDSCKSELA;
2942 typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
2943 	TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK           = 0x0,
2944 	TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK             = 0x1,
2945 } TMDS_TRANSMITTER_CONTROL_IDSCKSELB;
2946 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
2947 	TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE           = 0x0,
2948 	TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE            = 0x1,
2949 } TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN;
2950 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
2951 	TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD              = 0x0,
2952 	TMDS_TRANSMITTER_PLL_RST_ON_HPD                  = 0x1,
2953 } TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK;
2954 typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
2955 	TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK           = 0x0,
2956 	TMDS_TRANSMITTER_TMCLK_FROM_PADS                 = 0x1,
2957 } TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS;
2958 typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
2959 	TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK           = 0x0,
2960 	TMDS_TRANSMITTER_TDCLK_FROM_PADS                 = 0x1,
2961 } TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS;
2962 typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
2963 	TMDS_TRANSMITTER_PLLSEL_BY_HW                    = 0x0,
2964 	TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW          = 0x1,
2965 } TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN;
2966 typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
2967 	TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT            = 0x0,
2968 	TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT          = 0x1,
2969 } TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA;
2970 typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
2971 	TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT            = 0x0,
2972 	TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT          = 0x1,
2973 } TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB;
2974 typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
2975 	TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0              = 0x0,
2976 	TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1              = 0x1,
2977 	TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2              = 0x2,
2978 	TMDS_REG_TEST_OUTPUTA_CNTLA_NA                   = 0x3,
2979 } TMDS_REG_TEST_OUTPUTA_CNTLA;
2980 typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
2981 	TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0              = 0x0,
2982 	TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1              = 0x1,
2983 	TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2              = 0x2,
2984 	TMDS_REG_TEST_OUTPUTB_CNTLB_NA                   = 0x3,
2985 } TMDS_REG_TEST_OUTPUTB_CNTLB;
2986 typedef enum DP_LINK_TRAINING_COMPLETE {
2987 	DP_LINK_TRAINING_NOT_COMPLETE                    = 0x0,
2988 	DP_LINK_TRAINING_ALREADY_COMPLETE                = 0x1,
2989 } DP_LINK_TRAINING_COMPLETE;
2990 typedef enum DP_EMBEDDED_PANEL_MODE {
2991 	DP_EXTERNAL_PANEL                                = 0x0,
2992 	DP_EMBEDDED_PANEL                                = 0x1,
2993 } DP_EMBEDDED_PANEL_MODE;
2994 typedef enum DP_PIXEL_ENCODING {
2995 	DP_PIXEL_ENCODING_RGB444                         = 0x0,
2996 	DP_PIXEL_ENCODING_YCBCR422                       = 0x1,
2997 	DP_PIXEL_ENCODING_YCBCR444                       = 0x2,
2998 	DP_PIXEL_ENCODING_RGB_WIDE_GAMUT                 = 0x3,
2999 	DP_PIXEL_ENCODING_Y_ONLY                         = 0x4,
3000 	DP_PIXEL_ENCODING_YCBCR420                       = 0x5,
3001 	DP_PIXEL_ENCODING_RESERVED                       = 0x6,
3002 } DP_PIXEL_ENCODING;
3003 typedef enum DP_DYN_RANGE {
3004 	DP_DYN_VESA_RANGE                                = 0x0,
3005 	DP_DYN_CEA_RANGE                                 = 0x1,
3006 } DP_DYN_RANGE;
3007 typedef enum DP_YCBCR_RANGE {
3008 	DP_YCBCR_RANGE_BT601_5                           = 0x0,
3009 	DP_YCBCR_RANGE_BT709_5                           = 0x1,
3010 } DP_YCBCR_RANGE;
3011 typedef enum DP_COMPONENT_DEPTH {
3012 	DP_COMPONENT_DEPTH_6BPC                          = 0x0,
3013 	DP_COMPONENT_DEPTH_8BPC                          = 0x1,
3014 	DP_COMPONENT_DEPTH_10BPC                         = 0x2,
3015 	DP_COMPONENT_DEPTH_12BPC                         = 0x3,
3016 	DP_COMPONENT_DEPTH_16BPC                         = 0x4,
3017 	DP_COMPONENT_DEPTH_RESERVED                      = 0x5,
3018 } DP_COMPONENT_DEPTH;
3019 typedef enum DP_MSA_MISC0_OVERRIDE_ENABLE {
3020 	MSA_MISC0_OVERRIDE_DISABLE                       = 0x0,
3021 	MSA_MISC0_OVERRIDE_ENABLE                        = 0x1,
3022 } DP_MSA_MISC0_OVERRIDE_ENABLE;
3023 typedef enum DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE {
3024 	MSA_MISC1_BIT7_OVERRIDE_DISABLE                  = 0x0,
3025 	MSA_MISC1_BIT7_OVERRIDE_ENABLE                   = 0x1,
3026 } DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE;
3027 typedef enum DP_UDI_LANES {
3028 	DP_UDI_1_LANE                                    = 0x0,
3029 	DP_UDI_2_LANES                                   = 0x1,
3030 	DP_UDI_LANES_RESERVED                            = 0x2,
3031 	DP_UDI_4_LANES                                   = 0x3,
3032 } DP_UDI_LANES;
3033 typedef enum DP_VID_STREAM_DIS_DEFER {
3034 	DP_VID_STREAM_DIS_NO_DEFER                       = 0x0,
3035 	DP_VID_STREAM_DIS_DEFER_TO_HBLANK                = 0x1,
3036 	DP_VID_STREAM_DIS_DEFER_TO_VBLANK                = 0x2,
3037 } DP_VID_STREAM_DIS_DEFER;
3038 typedef enum DP_STEER_OVERFLOW_ACK {
3039 	DP_STEER_OVERFLOW_ACK_NO_EFFECT                  = 0x0,
3040 	DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT              = 0x1,
3041 } DP_STEER_OVERFLOW_ACK;
3042 typedef enum DP_STEER_OVERFLOW_MASK {
3043 	DP_STEER_OVERFLOW_MASKED                         = 0x0,
3044 	DP_STEER_OVERFLOW_UNMASK                         = 0x1,
3045 } DP_STEER_OVERFLOW_MASK;
3046 typedef enum DP_TU_OVERFLOW_ACK {
3047 	DP_TU_OVERFLOW_ACK_NO_EFFECT                     = 0x0,
3048 	DP_TU_OVERFLOW_ACK_CLR_INTERRUPT                 = 0x1,
3049 } DP_TU_OVERFLOW_ACK;
3050 typedef enum DP_VID_TIMING_MODE {
3051 	DP_VID_TIMING_MODE_ASYNC                         = 0x0,
3052 	DP_VID_TIMING_MODE_SYNC                          = 0x1,
3053 } DP_VID_TIMING_MODE;
3054 typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
3055 	DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE      = 0x0,
3056 	DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START          = 0x1,
3057 } DP_VID_M_N_DOUBLE_BUFFER_MODE;
3058 typedef enum DP_VID_M_N_GEN_EN {
3059 	DP_VID_M_N_PROGRAMMED_VIA_REG                    = 0x0,
3060 	DP_VID_M_N_CALC_AUTO                             = 0x1,
3061 } DP_VID_M_N_GEN_EN;
3062 typedef enum DP_VID_M_DOUBLE_VALUE_EN {
3063 	DP_VID_M_INPUT_PIXEL_RATE                        = 0x0,
3064 	DP_VID_M_DOUBLE_INPUT_PIXEL_RATE                 = 0x1,
3065 } DP_VID_M_DOUBLE_VALUE_EN;
3066 typedef enum DP_VID_ENHANCED_FRAME_MODE {
3067 	VID_NORMAL_FRAME_MODE                            = 0x0,
3068 	VID_ENHANCED_MODE                                = 0x1,
3069 } DP_VID_ENHANCED_FRAME_MODE;
3070 typedef enum DP_VID_MSA_TOP_FIELD_MODE {
3071 	DP_TOP_FIELD_ONLY                                = 0x0,
3072 	DP_TOP_PLUS_BOTTOM_FIELD                         = 0x1,
3073 } DP_VID_MSA_TOP_FIELD_MODE;
3074 typedef enum DP_VID_VBID_FIELD_POL {
3075 	DP_VID_VBID_FIELD_POL_NORMAL                     = 0x0,
3076 	DP_VID_VBID_FIELD_POL_INV                        = 0x1,
3077 } DP_VID_VBID_FIELD_POL;
3078 typedef enum DP_VID_STREAM_DISABLE_ACK {
3079 	ID_STREAM_DISABLE_NO_ACK                         = 0x0,
3080 	ID_STREAM_DISABLE_ACKED                          = 0x1,
3081 } DP_VID_STREAM_DISABLE_ACK;
3082 typedef enum DP_VID_STREAM_DISABLE_MASK {
3083 	VID_STREAM_DISABLE_MASKED                        = 0x0,
3084 	VID_STREAM_DISABLE_UNMASK                        = 0x1,
3085 } DP_VID_STREAM_DISABLE_MASK;
3086 typedef enum DPHY_ATEST_SEL_LANE0 {
3087 	DPHY_ATEST_LANE0_PRBS_PATTERN                    = 0x0,
3088 	DPHY_ATEST_LANE0_REG_PATTERN                     = 0x1,
3089 } DPHY_ATEST_SEL_LANE0;
3090 typedef enum DPHY_ATEST_SEL_LANE1 {
3091 	DPHY_ATEST_LANE1_PRBS_PATTERN                    = 0x0,
3092 	DPHY_ATEST_LANE1_REG_PATTERN                     = 0x1,
3093 } DPHY_ATEST_SEL_LANE1;
3094 typedef enum DPHY_ATEST_SEL_LANE2 {
3095 	DPHY_ATEST_LANE2_PRBS_PATTERN                    = 0x0,
3096 	DPHY_ATEST_LANE2_REG_PATTERN                     = 0x1,
3097 } DPHY_ATEST_SEL_LANE2;
3098 typedef enum DPHY_ATEST_SEL_LANE3 {
3099 	DPHY_ATEST_LANE3_PRBS_PATTERN                    = 0x0,
3100 	DPHY_ATEST_LANE3_REG_PATTERN                     = 0x1,
3101 } DPHY_ATEST_SEL_LANE3;
3102 typedef enum DPHY_BYPASS {
3103 	DPHY_8B10B_OUTPUT                                = 0x0,
3104 	DPHY_DBG_OUTPUT                                  = 0x1,
3105 } DPHY_BYPASS;
3106 typedef enum DPHY_SKEW_BYPASS {
3107 	DPHY_WITH_SKEW                                   = 0x0,
3108 	DPHY_NO_SKEW                                     = 0x1,
3109 } DPHY_SKEW_BYPASS;
3110 typedef enum DPHY_TRAINING_PATTERN_SEL {
3111 	DPHY_TRAINING_PATTERN_1                          = 0x0,
3112 	DPHY_TRAINING_PATTERN_2                          = 0x1,
3113 	DPHY_TRAINING_PATTERN_3                          = 0x2,
3114 	DPHY_TRAINING_PATTERN_4                          = 0x3,
3115 } DPHY_TRAINING_PATTERN_SEL;
3116 typedef enum DPHY_8B10B_RESET {
3117 	DPHY_8B10B_NOT_RESET                             = 0x0,
3118 	DPHY_8B10B_RESETET                               = 0x1,
3119 } DPHY_8B10B_RESET;
3120 typedef enum DP_DPHY_8B10B_EXT_DISP {
3121 	DP_DPHY_8B10B_EXT_DISP_ZERO                      = 0x0,
3122 	DP_DPHY_8B10B_EXT_DISP_ONE                       = 0x1,
3123 } DP_DPHY_8B10B_EXT_DISP;
3124 typedef enum DPHY_8B10B_CUR_DISP {
3125 	DPHY_8B10B_CUR_DISP_ZERO                         = 0x0,
3126 	DPHY_8B10B_CUR_DISP_ONE                          = 0x1,
3127 } DPHY_8B10B_CUR_DISP;
3128 typedef enum DPHY_PRBS_EN {
3129 	DPHY_PRBS_DISABLE                                = 0x0,
3130 	DPHY_PRBS_ENABLE                                 = 0x1,
3131 } DPHY_PRBS_EN;
3132 typedef enum DPHY_PRBS_SEL {
3133 	DPHY_PRBS7_SELECTED                              = 0x0,
3134 	DPHY_PRBS23_SELECTED                             = 0x1,
3135 	DPHY_PRBS11_SELECTED                             = 0x2,
3136 } DPHY_PRBS_SEL;
3137 typedef enum DPHY_LOAD_BS_COUNT_START {
3138 	DPHY_LOAD_BS_COUNT_STARTED                       = 0x0,
3139 	DPHY_LOAD_BS_COUNT_NOT_STARTED                   = 0x1,
3140 } DPHY_LOAD_BS_COUNT_START;
3141 typedef enum DPHY_CRC_EN {
3142 	DPHY_CRC_DISABLED                                = 0x0,
3143 	DPHY_CRC_ENABLED                                 = 0x1,
3144 } DPHY_CRC_EN;
3145 typedef enum DPHY_CRC_CONT_EN {
3146 	DPHY_CRC_ONE_SHOT                                = 0x0,
3147 	DPHY_CRC_CONTINUOUS                              = 0x1,
3148 } DPHY_CRC_CONT_EN;
3149 typedef enum DPHY_CRC_FIELD {
3150 	DPHY_CRC_START_FROM_TOP_FIELD                    = 0x0,
3151 	DPHY_CRC_START_FROM_BOTTOM_FIELD                 = 0x1,
3152 } DPHY_CRC_FIELD;
3153 typedef enum DPHY_CRC_SEL {
3154 	DPHY_CRC_LANE0_SELECTED                          = 0x0,
3155 	DPHY_CRC_LANE1_SELECTED                          = 0x1,
3156 	DPHY_CRC_LANE2_SELECTED                          = 0x2,
3157 	DPHY_CRC_LANE3_SELECTED                          = 0x3,
3158 } DPHY_CRC_SEL;
3159 typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
3160 	DPHY_FAST_TRAINING_NOT_CAPABLE_0                 = 0x0,
3161 	DPHY_FAST_TRAINING_CAPABLE                       = 0x1,
3162 } DPHY_RX_FAST_TRAINING_CAPABLE;
3163 typedef enum DP_SEC_COLLISION_ACK {
3164 	DP_SEC_COLLISION_ACK_NO_EFFECT                   = 0x0,
3165 	DP_SEC_COLLISION_ACK_CLR_FLAG                    = 0x1,
3166 } DP_SEC_COLLISION_ACK;
3167 typedef enum DP_SEC_AUDIO_MUTE {
3168 	DP_SEC_AUDIO_MUTE_HW_CTRL                        = 0x0,
3169 	DP_SEC_AUDIO_MUTE_SW_CTRL                        = 0x1,
3170 } DP_SEC_AUDIO_MUTE;
3171 typedef enum DP_SEC_TIMESTAMP_MODE {
3172 	DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE               = 0x0,
3173 	DP_SEC_TIMESTAMP_AUTO_CALC_MODE                  = 0x1,
3174 } DP_SEC_TIMESTAMP_MODE;
3175 typedef enum DP_SEC_ASP_PRIORITY {
3176 	DP_SEC_ASP_LOW_PRIORITY                          = 0x0,
3177 	DP_SEC_ASP_HIGH_PRIORITY                         = 0x1,
3178 } DP_SEC_ASP_PRIORITY;
3179 typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
3180 	DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ                 = 0x0,
3181 	DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED        = 0x1,
3182 } DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE;
3183 typedef enum DP_MSE_SAT_UPDATE_ACT {
3184 	DP_MSE_SAT_UPDATE_NO_ACTION                      = 0x0,
3185 	DP_MSE_SAT_UPDATE_WITH_TRIGGER                   = 0x1,
3186 	DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER                = 0x2,
3187 } DP_MSE_SAT_UPDATE_ACT;
3188 typedef enum DP_MSE_LINK_LINE {
3189 	DP_MSE_LINK_LINE_32_MTP_LONG                     = 0x0,
3190 	DP_MSE_LINK_LINE_64_MTP_LONG                     = 0x1,
3191 	DP_MSE_LINK_LINE_128_MTP_LONG                    = 0x2,
3192 	DP_MSE_LINK_LINE_256_MTP_LONG                    = 0x3,
3193 } DP_MSE_LINK_LINE;
3194 typedef enum DP_MSE_BLANK_CODE {
3195 	DP_MSE_BLANK_CODE_SF_FILLED                      = 0x0,
3196 	DP_MSE_BLANK_CODE_ZERO_FILLED                    = 0x1,
3197 } DP_MSE_BLANK_CODE;
3198 typedef enum DP_MSE_TIMESTAMP_MODE {
3199 	DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE         = 0x0,
3200 	DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE           = 0x1,
3201 } DP_MSE_TIMESTAMP_MODE;
3202 typedef enum DP_MSE_ZERO_ENCODER {
3203 	DP_MSE_NOT_ZERO_FE_ENCODER                       = 0x0,
3204 	DP_MSE_ZERO_FE_ENCODER                           = 0x1,
3205 } DP_MSE_ZERO_ENCODER;
3206 typedef enum DP_MSE_OUTPUT_DPDBG_DATA {
3207 	DP_MSE_OUTPUT_DPDBG_DATA_DIS                     = 0x0,
3208 	DP_MSE_OUTPUT_DPDBG_DATA_EN                      = 0x1,
3209 } DP_MSE_OUTPUT_DPDBG_DATA;
3210 typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
3211 	DP_DPHY_HBR2_PASS_THROUGH                        = 0x0,
3212 	DP_DPHY_HBR2_PATTERN_1                           = 0x1,
3213 	DP_DPHY_HBR2_PATTERN_2_NEG                       = 0x2,
3214 	DP_DPHY_HBR2_PATTERN_3                           = 0x3,
3215 	DP_DPHY_HBR2_PATTERN_2_POS                       = 0x6,
3216 } DP_DPHY_HBR2_PATTERN_CONTROL_MODE;
3217 typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
3218 	DPHY_CRC_MST_PHASE_ERROR_NO_ACK                  = 0x0,
3219 	DPHY_CRC_MST_PHASE_ERROR_ACKED                   = 0x1,
3220 } DPHY_CRC_MST_PHASE_ERROR_ACK;
3221 typedef enum DPHY_SW_FAST_TRAINING_START {
3222 	DPHY_SW_FAST_TRAINING_NOT_STARTED                = 0x0,
3223 	DPHY_SW_FAST_TRAINING_STARTED                    = 0x1,
3224 } DPHY_SW_FAST_TRAINING_START;
3225 typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
3226 	DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED= 0x0,
3227 	DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x1,
3228 } DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN;
3229 typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
3230 	DP_DPHY_FAST_TRAINING_COMPLETE_MASKED            = 0x0,
3231 	DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED        = 0x1,
3232 } DP_DPHY_FAST_TRAINING_COMPLETE_MASK;
3233 typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
3234 	DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED         = 0x0,
3235 	DP_DPHY_FAST_TRAINING_COMPLETE_ACKED             = 0x1,
3236 } DP_DPHY_FAST_TRAINING_COMPLETE_ACK;
3237 typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
3238 	MSA_V_TIMING_OVERRIDE_DISABLED                   = 0x0,
3239 	MSA_V_TIMING_OVERRIDE_ENABLED                    = 0x1,
3240 } DP_MSA_V_TIMING_OVERRIDE_EN;
3241 typedef enum DP_SEC_GSP0_PRIORITY {
3242 	SEC_GSP0_PRIORITY_LOW                            = 0x0,
3243 	SEC_GSP0_PRIORITY_HIGH                           = 0x1,
3244 } DP_SEC_GSP0_PRIORITY;
3245 typedef enum DP_SEC_GSP0_SEND {
3246 	NOT_SENT                                         = 0x0,
3247 	FORCE_SENT                                       = 0x1,
3248 } DP_SEC_GSP0_SEND;
3249 typedef enum DP_AUX_CONTROL_HPD_SEL {
3250 	DP_AUX_CONTROL_HPD1_SELECTED                     = 0x0,
3251 	DP_AUX_CONTROL_HPD2_SELECTED                     = 0x1,
3252 	DP_AUX_CONTROL_HPD3_SELECTED                     = 0x2,
3253 	DP_AUX_CONTROL_HPD4_SELECTED                     = 0x3,
3254 	DP_AUX_CONTROL_HPD5_SELECTED                     = 0x4,
3255 	DP_AUX_CONTROL_HPD6_SELECTED                     = 0x5,
3256 } DP_AUX_CONTROL_HPD_SEL;
3257 typedef enum DP_AUX_CONTROL_TEST_MODE {
3258 	DP_AUX_CONTROL_TEST_MODE_DISABLE                 = 0x0,
3259 	DP_AUX_CONTROL_TEST_MODE_ENABLE                  = 0x1,
3260 } DP_AUX_CONTROL_TEST_MODE;
3261 typedef enum DP_AUX_SW_CONTROL_SW_GO {
3262 	DP_AUX_SW_CONTROL_SW__NOT_GO                     = 0x0,
3263 	DP_AUX_SW_CONTROL_SW__GO                         = 0x1,
3264 } DP_AUX_SW_CONTROL_SW_GO;
3265 typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
3266 	DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG              = 0x0,
3267 	DP_AUX_SW_CONTROL_LS_READ__TRIG                  = 0x1,
3268 } DP_AUX_SW_CONTROL_LS_READ_TRIG;
3269 typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
3270 	DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW       = 0x0,
3271 	DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW       = 0x1,
3272 	DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC       = 0x2,
3273 	DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS       = 0x3,
3274 } DP_AUX_ARB_CONTROL_ARB_PRIORITY;
3275 typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
3276 	DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ          = 0x0,
3277 	DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ              = 0x1,
3278 } DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ;
3279 typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
3280 	DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG       = 0x0,
3281 	DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG           = 0x1,
3282 } DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG;
3283 typedef enum DP_AUX_INT_ACK {
3284 	DP_AUX_INT__NOT_ACK                              = 0x0,
3285 	DP_AUX_INT__ACK                                  = 0x1,
3286 } DP_AUX_INT_ACK;
3287 typedef enum DP_AUX_LS_UPDATE_ACK {
3288 	DP_AUX_INT_LS_UPDATE_NOT_ACK                     = 0x0,
3289 	DP_AUX_INT_LS_UPDATE_ACK                         = 0x1,
3290 } DP_AUX_LS_UPDATE_ACK;
3291 typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
3292 	DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK= 0x0,
3293 	DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF= 0x1,
3294 } DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL;
3295 typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
3296 	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ         = 0x0,
3297 	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ         = 0x1,
3298 	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ         = 0x2,
3299 	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ         = 0x3,
3300 } DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE;
3301 typedef enum DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN {
3302 	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US        = 0x0,
3303 	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US        = 0x1,
3304 	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US       = 0x2,
3305 	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US       = 0x3,
3306 	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US       = 0x4,
3307 	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US       = 0x5,
3308 	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US       = 0x6,
3309 	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US       = 0x7,
3310 } DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN;
3311 typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
3312 	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0   = 0x0,
3313 	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US= 0x1,
3314 	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US= 0x2,
3315 	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US= 0x3,
3316 	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US= 0x4,
3317 	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US= 0x5,
3318 } DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY;
3319 typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
3320 	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x0,
3321 	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x1,
3322 	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x2,
3323 	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD= 0x3,
3324 	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD= 0x4,
3325 	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD= 0x5,
3326 	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD= 0x6,
3327 	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD= 0x7,
3328 } DP_AUX_DPHY_RX_CONTROL_START_WINDOW;
3329 typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
3330 	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD= 0x0,
3331 	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD= 0x1,
3332 	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD= 0x2,
3333 	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD= 0x3,
3334 	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD= 0x4,
3335 	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD= 0x5,
3336 	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD= 0x6,
3337 	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD= 0x7,
3338 } DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW;
3339 typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
3340 	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES= 0x0,
3341 	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES= 0x1,
3342 	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES= 0x2,
3343 	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED= 0x3,
3344 } DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN;
3345 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
3346 	DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x0,
3347 	DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x1,
3348 } DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT;
3349 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
3350 	DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START= 0x0,
3351 	DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START= 0x1,
3352 } DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START;
3353 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
3354 	DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP= 0x0,
3355 	DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP= 0x1,
3356 } DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP;
3357 typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
3358 	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS= 0x0,
3359 	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS= 0x1,
3360 	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS= 0x2,
3361 	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS= 0x3,
3362 } DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN;
3363 typedef enum DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN {
3364 	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US         = 0x0,
3365 	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US         = 0x1,
3366 	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US         = 0x2,
3367 	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US         = 0x3,
3368 	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US         = 0x4,
3369 	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US         = 0x5,
3370 	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US         = 0x6,
3371 	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US         = 0x7,
3372 } DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN;
3373 typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
3374 	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2         = 0x0,
3375 	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4         = 0x1,
3376 	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8         = 0x2,
3377 	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16       = 0x3,
3378 	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32       = 0x4,
3379 	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64       = 0x5,
3380 	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128     = 0x6,
3381 	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256     = 0x7,
3382 } DP_AUX_DPHY_RX_DETECTION_THRESHOLD;
3383 typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
3384 	DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX= 0x0,
3385 	DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX= 0x1,
3386 } DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ;
3387 typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
3388 	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US= 0x0,
3389 	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US= 0x1,
3390 	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US= 0x2,
3391 	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US= 0x3,
3392 } DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW;
3393 typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
3394 	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS= 0x0,
3395 	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS= 0x1,
3396 	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS= 0x2,
3397 	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED= 0x3,
3398 } DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT;
3399 typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
3400 	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0= 0x0,
3401 	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64= 0x1,
3402 	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128= 0x2,
3403 	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256= 0x3,
3404 } DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN;
3405 typedef enum DP_AUX_ERR_OCCURRED_ACK {
3406 	DP_AUX_ERR_OCCURRED__NOT_ACK                     = 0x0,
3407 	DP_AUX_ERR_OCCURRED__ACK                         = 0x1,
3408 } DP_AUX_ERR_OCCURRED_ACK;
3409 typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
3410 	DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK            = 0x0,
3411 	DP_AUX_POTENTIAL_ERR_REACHED__ACK                = 0x1,
3412 } DP_AUX_POTENTIAL_ERR_REACHED_ACK;
3413 typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
3414 	ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK        = 0x0,
3415 	ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK            = 0x1,
3416 } DP_AUX_DEFINITE_ERR_REACHED_ACK;
3417 typedef enum DP_AUX_RESET {
3418 	DP_AUX_RESET_DEASSERTED                          = 0x0,
3419 	DP_AUX_RESET_ASSERTED                            = 0x1,
3420 } DP_AUX_RESET;
3421 typedef enum DP_AUX_RESET_DONE {
3422 	DP_AUX_RESET_SEQUENCE_NOT_DONE                   = 0x0,
3423 	DP_AUX_RESET_SEQUENCE_DONE                       = 0x1,
3424 } DP_AUX_RESET_DONE;
3425 typedef enum FBC_IDLE_MASK_MASK_BITS {
3426 	FBC_IDLE_MASK_DISP_REG_UPDATE                    = 0x0,
3427 	FBC_IDLE_MASK_RESERVED1                          = 0x1,
3428 	FBC_IDLE_MASK_FBC_GRPH_COMP_EN                   = 0x2,
3429 	FBC_IDLE_MASK_FBC_MIN_COMPRESSION                = 0x3,
3430 	FBC_IDLE_MASK_FBC_ALPHA_COMP_EN                  = 0x4,
3431 	FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN       = 0x5,
3432 	FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF         = 0x6,
3433 	FBC_IDLE_MASK_RESERVED7                          = 0x7,
3434 	FBC_IDLE_MASK_RESERVED8                          = 0x8,
3435 	FBC_IDLE_MASK_RESERVED9                          = 0x9,
3436 	FBC_IDLE_MASK_RESERVED10                         = 0xa,
3437 	FBC_IDLE_MASK_RESERVED11                         = 0xb,
3438 	FBC_IDLE_MASK_RESERVED12                         = 0xc,
3439 	FBC_IDLE_MASK_RESERVED13                         = 0xd,
3440 	FBC_IDLE_MASK_RESERVED14                         = 0xe,
3441 	FBC_IDLE_MASK_RESERVED15                         = 0xf,
3442 	FBC_IDLE_MASK_RESERVED16                         = 0x10,
3443 	FBC_IDLE_MASK_RESERVED17                         = 0x11,
3444 	FBC_IDLE_MASK_RESERVED18                         = 0x12,
3445 	FBC_IDLE_MASK_RESERVED19                         = 0x13,
3446 	FBC_IDLE_MASK_RESERVED20                         = 0x14,
3447 	FBC_IDLE_MASK_RESERVED21                         = 0x15,
3448 	FBC_IDLE_MASK_RESERVED22                         = 0x16,
3449 	FBC_IDLE_MASK_RESERVED23                         = 0x17,
3450 	FBC_IDLE_MASK_MC_HIT_REGION_0                    = 0x18,
3451 	FBC_IDLE_MASK_MC_HIT_REGION_1                    = 0x19,
3452 	FBC_IDLE_MASK_MC_HIT_REGION_2                    = 0x1a,
3453 	FBC_IDLE_MASK_MC_HIT_REGION_3                    = 0x1b,
3454 	FBC_IDLE_MASK_MC_WRITE                           = 0x1c,
3455 	FBC_IDLE_MASK_CG_STATIC_SCREEN                   = 0x1d,
3456 	FBC_IDLE_MASK_RESERVED30                         = 0x1e,
3457 	FBC_IDLE_MASK_RESERVED31                         = 0x1f,
3458 } FBC_IDLE_MASK_MASK_BITS;
3459 typedef enum FMT_CONTROL_PIXEL_ENCODING {
3460 	FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444    = 0x0,
3461 	FMT_CONTROL_PIXEL_ENCODING_YCBCR422              = 0x1,
3462 	FMT_CONTROL_PIXEL_ENCODING_YCBCR420              = 0x2,
3463 	FMT_CONTROL_PIXEL_ENCODING_RESERVED              = 0x3,
3464 } FMT_CONTROL_PIXEL_ENCODING;
3465 typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
3466 	FMT_CONTROL_SUBSAMPLING_MODE_DROP                = 0x0,
3467 	FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE             = 0x1,
3468 	FMT_CONTROL_SUBSAMPLING_MODE_3_TAP               = 0x2,
3469 	FMT_CONTROL_SUBSAMPLING_MODE_RESERVED            = 0x3,
3470 } FMT_CONTROL_SUBSAMPLING_MODE;
3471 typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
3472 	FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR       = 0x0,
3473 	FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB       = 0x1,
3474 } FMT_CONTROL_SUBSAMPLING_ORDER;
3475 typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
3476 	FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE    = 0x0,
3477 	FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE     = 0x1,
3478 } FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS;
3479 typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
3480 	FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION   = 0x0,
3481 	FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING     = 0x1,
3482 } FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;
3483 typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
3484 	FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP       = 0x0,
3485 	FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP       = 0x1,
3486 	FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP       = 0x2,
3487 } FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;
3488 typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
3489 	FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x0,
3490 	FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x1,
3491 	FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x2,
3492 } FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;
3493 typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
3494 	FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP= 0x0,
3495 	FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP= 0x1,
3496 	FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP= 0x2,
3497 } FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;
3498 typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
3499 	FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x0,
3500 	FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x1,
3501 } FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;
3502 typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
3503 	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei               = 0x0,
3504 	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi               = 0x1,
3505 	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi               = 0x2,
3506 	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED         = 0x3,
3507 } FMT_BIT_DEPTH_CONTROL_25FRC_SEL;
3508 typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
3509 	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A                = 0x0,
3510 	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B                = 0x1,
3511 	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C                = 0x2,
3512 	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D                = 0x3,
3513 } FMT_BIT_DEPTH_CONTROL_50FRC_SEL;
3514 typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
3515 	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E                = 0x0,
3516 	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F                = 0x1,
3517 	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G                = 0x2,
3518 	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED         = 0x3,
3519 } FMT_BIT_DEPTH_CONTROL_75FRC_SEL;
3520 typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT {
3521 	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN= 0x0,
3522 	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN= 0x1,
3523 } FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT;
3524 typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
3525 	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR= 0x0,
3526 	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB= 0x1,
3527 } FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;
3528 typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
3529 	FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC                 = 0x0,
3530 	FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC                 = 0x1,
3531 	FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC                = 0x2,
3532 	FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC                = 0x3,
3533 	FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1            = 0x4,
3534 	FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2            = 0x5,
3535 	FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3            = 0x6,
3536 	FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE         = 0x7,
3537 } FMT_CLAMP_CNTL_COLOR_FORMAT;
3538 typedef enum FMT_CRC_CNTL_CONT_EN {
3539 	FMT_CRC_CNTL_CONT_EN_ONE_SHOT                    = 0x0,
3540 	FMT_CRC_CNTL_CONT_EN_CONT                        = 0x1,
3541 } FMT_CRC_CNTL_CONT_EN;
3542 typedef enum FMT_CRC_CNTL_INCLUDE_OVERSCAN {
3543 	FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE        = 0x0,
3544 	FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE            = 0x1,
3545 } FMT_CRC_CNTL_INCLUDE_OVERSCAN;
3546 typedef enum FMT_CRC_CNTL_ONLY_BLANKB {
3547 	FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD            = 0x0,
3548 	FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK               = 0x1,
3549 } FMT_CRC_CNTL_ONLY_BLANKB;
3550 typedef enum FMT_CRC_CNTL_PSR_MODE_ENABLE {
3551 	FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL              = 0x0,
3552 	FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC         = 0x1,
3553 } FMT_CRC_CNTL_PSR_MODE_ENABLE;
3554 typedef enum FMT_CRC_CNTL_INTERLACE_MODE {
3555 	FMT_CRC_CNTL_INTERLACE_MODE_TOP                  = 0x0,
3556 	FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM               = 0x1,
3557 	FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM          = 0x2,
3558 	FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH            = 0x3,
3559 } FMT_CRC_CNTL_INTERLACE_MODE;
3560 typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE {
3561 	FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL             = 0x0,
3562 	FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN        = 0x1,
3563 } FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE;
3564 typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT {
3565 	FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN            = 0x0,
3566 	FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD             = 0x1,
3567 } FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT;
3568 typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
3569 	FMT_DEBUG_CNTL_COLOR_SELECT_BLUE                 = 0x0,
3570 	FMT_DEBUG_CNTL_COLOR_SELECT_GREEN                = 0x1,
3571 	FMT_DEBUG_CNTL_COLOR_SELECT_RED1                 = 0x2,
3572 	FMT_DEBUG_CNTL_COLOR_SELECT_RED2                 = 0x3,
3573 } FMT_DEBUG_CNTL_COLOR_SELECT;
3574 typedef enum FMT_SPATIAL_DITHER_MODE {
3575 	FMT_SPATIAL_DITHER_MODE_0                        = 0x0,
3576 	FMT_SPATIAL_DITHER_MODE_1                        = 0x1,
3577 	FMT_SPATIAL_DITHER_MODE_2                        = 0x2,
3578 	FMT_SPATIAL_DITHER_MODE_3                        = 0x3,
3579 } FMT_SPATIAL_DITHER_MODE;
3580 typedef enum FMT_STEREOSYNC_OVR_POL {
3581 	FMT_STEREOSYNC_OVR_POL_INVERTED                  = 0x0,
3582 	FMT_STEREOSYNC_OVR_POL_NOT_INVERTED              = 0x1,
3583 } FMT_STEREOSYNC_OVR_POL;
3584 typedef enum FMT_DYNAMIC_EXP_MODE {
3585 	FMT_DYNAMIC_EXP_MODE_10to12                      = 0x0,
3586 	FMT_DYNAMIC_EXP_MODE_8to12                       = 0x1,
3587 } FMT_DYNAMIC_EXP_MODE;
3588 typedef enum LB_DATA_FORMAT_PIXEL_DEPTH {
3589 	LB_DATA_FORMAT_PIXEL_DEPTH_30BPP                 = 0x0,
3590 	LB_DATA_FORMAT_PIXEL_DEPTH_24BPP                 = 0x1,
3591 	LB_DATA_FORMAT_PIXEL_DEPTH_18BPP                 = 0x2,
3592 	LB_DATA_FORMAT_PIXEL_DEPTH_36BPP                 = 0x3,
3593 } LB_DATA_FORMAT_PIXEL_DEPTH;
3594 typedef enum LB_DATA_FORMAT_PIXEL_EXPAN_MODE {
3595 	LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION= 0x0,
3596 	LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION= 0x1,
3597 } LB_DATA_FORMAT_PIXEL_EXPAN_MODE;
3598 typedef enum LB_DATA_FORMAT_PIXEL_REDUCE_MODE {
3599 	LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION      = 0x0,
3600 	LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING        = 0x1,
3601 } LB_DATA_FORMAT_PIXEL_REDUCE_MODE;
3602 typedef enum LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH {
3603 	LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP         = 0x0,
3604 	LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP         = 0x1,
3605 } LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH;
3606 typedef enum LB_DATA_FORMAT_INTERLEAVE_EN {
3607 	LB_DATA_FORMAT_INTERLEAVE_DISABLE                = 0x0,
3608 	LB_DATA_FORMAT_INTERLEAVE_ENABLE                 = 0x1,
3609 } LB_DATA_FORMAT_INTERLEAVE_EN;
3610 typedef enum LB_DATA_FORMAT_PREFILL_EN {
3611 	LB_DATA_FORMAT_PREFILL_DISABLE                   = 0x0,
3612 	LB_DATA_FORMAT_PREFILL_ENABLE                    = 0x1,
3613 } LB_DATA_FORMAT_PREFILL_EN;
3614 typedef enum LB_DATA_FORMAT_REQUEST_MODE {
3615 	LB_DATA_FORMAT_REQUEST_MODE_NORMAL               = 0x0,
3616 	LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE        = 0x1,
3617 } LB_DATA_FORMAT_REQUEST_MODE;
3618 typedef enum LB_DATA_FORMAT_ALPHA_EN {
3619 	LB_DATA_FORMAT_ALPHA_DISABLE                     = 0x0,
3620 	LB_DATA_FORMAT_ALPHA_ENABLE                      = 0x1,
3621 } LB_DATA_FORMAT_ALPHA_EN;
3622 typedef enum LB_VLINE_START_END_VLINE_INV {
3623 	LB_VLINE_START_END_VLINE_NORMAL                  = 0x0,
3624 	LB_VLINE_START_END_VLINE_INVERSE                 = 0x1,
3625 } LB_VLINE_START_END_VLINE_INV;
3626 typedef enum LB_VLINE2_START_END_VLINE2_INV {
3627 	LB_VLINE2_START_END_VLINE2_NORMAL                = 0x0,
3628 	LB_VLINE2_START_END_VLINE2_INVERSE               = 0x1,
3629 } LB_VLINE2_START_END_VLINE2_INV;
3630 typedef enum LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK {
3631 	LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE       = 0x0,
3632 	LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE        = 0x1,
3633 } LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK;
3634 typedef enum LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK {
3635 	LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE        = 0x0,
3636 	LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE         = 0x1,
3637 } LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK;
3638 typedef enum LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK {
3639 	LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE       = 0x0,
3640 	LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE        = 0x1,
3641 } LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK;
3642 typedef enum LB_VLINE_STATUS_VLINE_ACK {
3643 	LB_VLINE_STATUS_VLINE_NORMAL                     = 0x0,
3644 	LB_VLINE_STATUS_VLINE_CLEAR                      = 0x1,
3645 } LB_VLINE_STATUS_VLINE_ACK;
3646 typedef enum LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE {
3647 	LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED = 0x0,
3648 	LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED = 0x1,
3649 } LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE;
3650 typedef enum LB_VLINE2_STATUS_VLINE2_ACK {
3651 	LB_VLINE2_STATUS_VLINE2_NORMAL                   = 0x0,
3652 	LB_VLINE2_STATUS_VLINE2_CLEAR                    = 0x1,
3653 } LB_VLINE2_STATUS_VLINE2_ACK;
3654 typedef enum LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE {
3655 	LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED= 0x0,
3656 	LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED= 0x1,
3657 } LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE;
3658 typedef enum LB_VBLANK_STATUS_VBLANK_ACK {
3659 	LB_VBLANK_STATUS_VBLANK_NORMAL                   = 0x0,
3660 	LB_VBLANK_STATUS_VBLANK_CLEAR                    = 0x1,
3661 } LB_VBLANK_STATUS_VBLANK_ACK;
3662 typedef enum LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE {
3663 	LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED= 0x0,
3664 	LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED= 0x1,
3665 } LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE;
3666 typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL {
3667 	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE      = 0x0,
3668 	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK= 0x1,
3669 	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET= 0x2,
3670 	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET= 0x3,
3671 } LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL;
3672 typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 {
3673 	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK  = 0x0,
3674 	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC   = 0x1,
3675 } LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2;
3676 typedef enum LB_SYNC_RESET_SEL_LB_SYNC_DURATION {
3677 	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS     = 0x0,
3678 	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS     = 0x1,
3679 	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS     = 0x2,
3680 	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS    = 0x3,
3681 } LB_SYNC_RESET_SEL_LB_SYNC_DURATION;
3682 typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN {
3683 	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE       = 0x0,
3684 	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE        = 0x1,
3685 } LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN;
3686 typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN {
3687 	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE= 0x0,
3688 	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE= 0x1,
3689 } LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN;
3690 typedef enum LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK {
3691 	LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL          = 0x0,
3692 	LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET           = 0x1,
3693 } LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK;
3694 typedef enum LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK {
3695 	LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL           = 0x0,
3696 	LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET            = 0x1,
3697 } LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK;
3698 typedef enum LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE {
3699 	LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP = 0x2,
3700 	LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP= 0x3,
3701 } LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE;
3702 typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET {
3703 	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL= 0x0,
3704 	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE= 0x1,
3705 } LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET;
3706 typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK {
3707 	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0= 0x0,
3708 	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1= 0x1,
3709 } LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK;
3710 typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE {
3711 	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT= 0x0,
3712 	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG= 0x1,
3713 	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE= 0x2,
3714 } LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE;
3715 typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE {
3716 	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE= 0x0,
3717 	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN     = 0x1,
3718 } LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE;
3719 typedef enum LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE {
3720 	ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER= 0x1,
3721 	ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE= 0x2,
3722 } LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE;
3723 typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL {
3724 	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0= 0x0,
3725 	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1= 0x1,
3726 } LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL;
3727 typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE {
3728 	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE= 0x0,
3729 	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE= 0x1,
3730 } LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE;
3731 typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO {
3732 	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO= 0x0,
3733 	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO= 0x1,
3734 } LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO;
3735 typedef enum LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN {
3736 	LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0= 0x0,
3737 	LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1= 0x1,
3738 } LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN;
3739 typedef enum LBV_PIXEL_DEPTH {
3740 	PIXEL_DEPTH_30BPP                                = 0x0,
3741 	PIXEL_DEPTH_24BPP                                = 0x1,
3742 	PIXEL_DEPTH_18BPP                                = 0x2,
3743 	PIXEL_DEPTH_38BPP                                = 0x3,
3744 } LBV_PIXEL_DEPTH;
3745 typedef enum LBV_PIXEL_EXPAN_MODE {
3746 	PIXEL_EXPAN_MODE_ZERO_EXP                        = 0x0,
3747 	PIXEL_EXPAN_MODE_DYN_EXP                         = 0x1,
3748 } LBV_PIXEL_EXPAN_MODE;
3749 typedef enum LBV_INTERLEAVE_EN {
3750 	INTERLEAVE_DIS                                   = 0x0,
3751 	INTERLEAVE_EN                                    = 0x1,
3752 } LBV_INTERLEAVE_EN;
3753 typedef enum LBV_PIXEL_REDUCE_MODE {
3754 	PIXEL_REDUCE_MODE_TRUNCATION                     = 0x0,
3755 	PIXEL_REDUCE_MODE_ROUNDING                       = 0x1,
3756 } LBV_PIXEL_REDUCE_MODE;
3757 typedef enum LBV_DYNAMIC_PIXEL_DEPTH {
3758 	DYNAMIC_PIXEL_DEPTH_36BPP                        = 0x0,
3759 	DYNAMIC_PIXEL_DEPTH_30BPP                        = 0x1,
3760 } LBV_DYNAMIC_PIXEL_DEPTH;
3761 typedef enum LBV_DITHER_EN {
3762 	DITHER_DIS                                       = 0x0,
3763 	DITHER_EN                                        = 0x1,
3764 } LBV_DITHER_EN;
3765 typedef enum LBV_DOWNSCALE_PREFETCH_EN {
3766 	DOWNSCALE_PREFETCH_DIS                           = 0x0,
3767 	DOWNSCALE_PREFETCH_EN                            = 0x1,
3768 } LBV_DOWNSCALE_PREFETCH_EN;
3769 typedef enum LBV_MEMORY_CONFIG {
3770 	MEMORY_CONFIG_0                                  = 0x0,
3771 	MEMORY_CONFIG_1                                  = 0x1,
3772 	MEMORY_CONFIG_2                                  = 0x2,
3773 	MEMORY_CONFIG_3                                  = 0x3,
3774 } LBV_MEMORY_CONFIG;
3775 typedef enum LBV_SYNC_RESET_SEL2 {
3776 	SYNC_RESET_SEL2_VBLANK                           = 0x0,
3777 	SYNC_RESET_SEL2_VSYNC                            = 0x1,
3778 } LBV_SYNC_RESET_SEL2;
3779 typedef enum LBV_SYNC_DURATION {
3780 	SYNC_DURATION_16                                 = 0x0,
3781 	SYNC_DURATION_32                                 = 0x1,
3782 	SYNC_DURATION_64                                 = 0x2,
3783 	SYNC_DURATION_128                                = 0x3,
3784 } LBV_SYNC_DURATION;
3785 typedef enum SCL_C_RAM_TAP_PAIR_IDX {
3786 	SCL_C_RAM_TAP_PAIR_ID0                           = 0x0,
3787 	SCL_C_RAM_TAP_PAIR_ID1                           = 0x1,
3788 	SCL_C_RAM_TAP_PAIR_ID2                           = 0x2,
3789 	SCL_C_RAM_TAP_PAIR_ID3                           = 0x3,
3790 	SCL_C_RAM_TAP_PAIR_ID4                           = 0x4,
3791 } SCL_C_RAM_TAP_PAIR_IDX;
3792 typedef enum SCL_C_RAM_PHASE {
3793 	SCL_C_RAM_PHASE_0                                = 0x0,
3794 	SCL_C_RAM_PHASE_1                                = 0x1,
3795 	SCL_C_RAM_PHASE_2                                = 0x2,
3796 	SCL_C_RAM_PHASE_3                                = 0x3,
3797 	SCL_C_RAM_PHASE_4                                = 0x4,
3798 	SCL_C_RAM_PHASE_5                                = 0x5,
3799 	SCL_C_RAM_PHASE_6                                = 0x6,
3800 	SCL_C_RAM_PHASE_7                                = 0x7,
3801 	SCL_C_RAM_PHASE_8                                = 0x8,
3802 } SCL_C_RAM_PHASE;
3803 typedef enum SCL_C_RAM_FILTER_TYPE {
3804 	SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT          = 0x0,
3805 	SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT            = 0x1,
3806 	SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT          = 0x2,
3807 	SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT            = 0x3,
3808 } SCL_C_RAM_FILTER_TYPE;
3809 typedef enum SCL_MODE_SEL {
3810 	SCL_MODE_RGB_BYPASS                              = 0x0,
3811 	SCL_MODE_RGB_SCALING                             = 0x1,
3812 	SCL_MODE_YCBCR_SCALING                           = 0x2,
3813 	SCL_MODE_YCBCR_BYPASS                            = 0x3,
3814 } SCL_MODE_SEL;
3815 typedef enum SCL_PSCL_EN {
3816 	SCL_PSCL_DISABLE                                 = 0x0,
3817 	SCL_PSCL_ENANBLE                                 = 0x1,
3818 } SCL_PSCL_EN;
3819 typedef enum SCL_V_NUM_OF_TAPS {
3820 	SCL_V_NUM_OF_TAPS_1                              = 0x0,
3821 	SCL_V_NUM_OF_TAPS_2                              = 0x1,
3822 	SCL_V_NUM_OF_TAPS_3                              = 0x2,
3823 	SCL_V_NUM_OF_TAPS_4                              = 0x3,
3824 	SCL_V_NUM_OF_TAPS_5                              = 0x4,
3825 	SCL_V_NUM_OF_TAPS_6                              = 0x5,
3826 } SCL_V_NUM_OF_TAPS;
3827 typedef enum SCL_H_NUM_OF_TAPS {
3828 	SCL_H_NUM_OF_TAPS_1                              = 0x0,
3829 	SCL_H_NUM_OF_TAPS_2                              = 0x1,
3830 	SCL_H_NUM_OF_TAPS_4                              = 0x3,
3831 	SCL_H_NUM_OF_TAPS_6                              = 0x5,
3832 	SCL_H_NUM_OF_TAPS_8                              = 0x7,
3833 	SCL_H_NUM_OF_TAPS_10                             = 0x9,
3834 } SCL_H_NUM_OF_TAPS;
3835 typedef enum SCL_BOUNDARY_MODE {
3836 	SCL_BOUNDARY_MODE_BLACK                          = 0x0,
3837 	SCL_BOUNDARY_MODE_EDGE                           = 0x1,
3838 } SCL_BOUNDARY_MODE;
3839 typedef enum SCL_EARLY_EOL_MOD {
3840 	SCL_EARLY_EOL_MODE_CRTC                          = 0x0,
3841 	SCL_EARLY_EOL_MODE_INTERNAL                      = 0x1,
3842 } SCL_EARLY_EOL_MOD;
3843 typedef enum SCL_BYPASS_MODE {
3844 	SCL_BYPASS_MODE_MC_MR                            = 0x0,
3845 	SCL_BYPASS_MODE_AC_NR                            = 0x1,
3846 	SCL_BYPASS_MODE_AC_AR                            = 0x2,
3847 	SCL_BYPASS_MODE_RESERVED                         = 0x3,
3848 } SCL_BYPASS_MODE;
3849 typedef enum SCL_V_MANUAL_REPLICATE_FACTOR {
3850 	SCL_V_MANUAL_REPLICATE_FACTOR_1                  = 0x0,
3851 	SCL_V_MANUAL_REPLICATE_FACTOR_2                  = 0x1,
3852 	SCL_V_MANUAL_REPLICATE_FACTOR_3                  = 0x2,
3853 	SCL_V_MANUAL_REPLICATE_FACTOR_4                  = 0x3,
3854 	SCL_V_MANUAL_REPLICATE_FACTOR_5                  = 0x4,
3855 	SCL_V_MANUAL_REPLICATE_FACTOR_6                  = 0x5,
3856 	SCL_V_MANUAL_REPLICATE_FACTOR_7                  = 0x6,
3857 	SCL_V_MANUAL_REPLICATE_FACTOR_8                  = 0x7,
3858 	SCL_V_MANUAL_REPLICATE_FACTOR_9                  = 0x8,
3859 	SCL_V_MANUAL_REPLICATE_FACTOR_10                 = 0x9,
3860 	SCL_V_MANUAL_REPLICATE_FACTOR_11                 = 0xa,
3861 	SCL_V_MANUAL_REPLICATE_FACTOR_12                 = 0xb,
3862 	SCL_V_MANUAL_REPLICATE_FACTOR_13                 = 0xc,
3863 	SCL_V_MANUAL_REPLICATE_FACTOR_14                 = 0xd,
3864 	SCL_V_MANUAL_REPLICATE_FACTOR_15                 = 0xe,
3865 	SCL_V_MANUAL_REPLICATE_FACTOR_16                 = 0xf,
3866 } SCL_V_MANUAL_REPLICATE_FACTOR;
3867 typedef enum SCL_H_MANUAL_REPLICATE_FACTOR {
3868 	SCL_H_MANUAL_REPLICATE_FACTOR_1                  = 0x0,
3869 	SCL_H_MANUAL_REPLICATE_FACTOR_2                  = 0x1,
3870 	SCL_H_MANUAL_REPLICATE_FACTOR_3                  = 0x2,
3871 	SCL_H_MANUAL_REPLICATE_FACTOR_4                  = 0x3,
3872 	SCL_H_MANUAL_REPLICATE_FACTOR_5                  = 0x4,
3873 	SCL_H_MANUAL_REPLICATE_FACTOR_6                  = 0x5,
3874 	SCL_H_MANUAL_REPLICATE_FACTOR_7                  = 0x6,
3875 	SCL_H_MANUAL_REPLICATE_FACTOR_8                  = 0x7,
3876 	SCL_H_MANUAL_REPLICATE_FACTOR_9                  = 0x8,
3877 	SCL_H_MANUAL_REPLICATE_FACTOR_10                 = 0x9,
3878 	SCL_H_MANUAL_REPLICATE_FACTOR_11                 = 0xa,
3879 	SCL_H_MANUAL_REPLICATE_FACTOR_12                 = 0xb,
3880 	SCL_H_MANUAL_REPLICATE_FACTOR_13                 = 0xc,
3881 	SCL_H_MANUAL_REPLICATE_FACTOR_14                 = 0xd,
3882 	SCL_H_MANUAL_REPLICATE_FACTOR_15                 = 0xe,
3883 	SCL_H_MANUAL_REPLICATE_FACTOR_16                 = 0xf,
3884 } SCL_H_MANUAL_REPLICATE_FACTOR;
3885 typedef enum SCL_V_CALC_AUTO_RATIO_EN {
3886 	SCL_V_CALC_AUTO_RATIO_DISABLE                    = 0x0,
3887 	SCL_V_CALC_AUTO_RATIO_ENABLE                     = 0x1,
3888 } SCL_V_CALC_AUTO_RATIO_EN;
3889 typedef enum SCL_H_CALC_AUTO_RATIO_EN {
3890 	SCL_H_CALC_AUTO_RATIO_DISABLE                    = 0x0,
3891 	SCL_H_CALC_AUTO_RATIO_ENABLE                     = 0x1,
3892 } SCL_H_CALC_AUTO_RATIO_EN;
3893 typedef enum SCL_H_FILTER_PICK_NEAREST {
3894 	SCL_H_FILTER_PICK_NEAREST_DISABLE                = 0x0,
3895 	SCL_H_FILTER_PICK_NEAREST_ENABLE                 = 0x1,
3896 } SCL_H_FILTER_PICK_NEAREST;
3897 typedef enum SCL_H_2TAP_HARDCODE_COEF_EN {
3898 	SCL_H_2TAP_HARDCODE_COEF_DISABLE                 = 0x0,
3899 	SCL_H_2TAP_HARDCODE_COEF_ENABLE                  = 0x1,
3900 } SCL_H_2TAP_HARDCODE_COEF_EN;
3901 typedef enum SCL_V_FILTER_PICK_NEAREST {
3902 	SCL_V_FILTER_PICK_NEAREST_DISABLE                = 0x0,
3903 	SCL_V_FILTER_PICK_NEAREST_ENABLE                 = 0x1,
3904 } SCL_V_FILTER_PICK_NEAREST;
3905 typedef enum SCL_V_2TAP_HARDCODE_COEF_EN {
3906 	SCL_V_2TAP_HARDCODE_COEF_DISABLE                 = 0x0,
3907 	SCL_V_2TAP_HARDCODE_COEF_ENABLE                  = 0x1,
3908 } SCL_V_2TAP_HARDCODE_COEF_EN;
3909 typedef enum SCL_UPDATE_TAKEN {
3910 	SCL_UPDATE_TAKEN_NO                              = 0x0,
3911 	SCL_UPDATE_TAKEN_YES                             = 0x1,
3912 } SCL_UPDATE_TAKEN;
3913 typedef enum SCL_UPDATE_LOCK {
3914 	SCL_UPDATE_UNLOCKED                              = 0x0,
3915 	SCL_UPDATE_LOCKED                                = 0x1,
3916 } SCL_UPDATE_LOCK;
3917 typedef enum SCL_COEF_UPDATE_COMPLETE {
3918 	SCL_COEF_UPDATE_NOT_COMPLETED                    = 0x0,
3919 	SCL_COEF_UPDATE_COMPLETED                        = 0x1,
3920 } SCL_COEF_UPDATE_COMPLETE;
3921 typedef enum SCL_HF_SHARP_SCALE_FACTOR {
3922 	SCL_HF_SHARP_SCALE_FACTOR_0                      = 0x0,
3923 	SCL_HF_SHARP_SCALE_FACTOR_1                      = 0x1,
3924 	SCL_HF_SHARP_SCALE_FACTOR_2                      = 0x2,
3925 	SCL_HF_SHARP_SCALE_FACTOR_3                      = 0x3,
3926 	SCL_HF_SHARP_SCALE_FACTOR_4                      = 0x4,
3927 	SCL_HF_SHARP_SCALE_FACTOR_5                      = 0x5,
3928 	SCL_HF_SHARP_SCALE_FACTOR_6                      = 0x6,
3929 	SCL_HF_SHARP_SCALE_FACTOR_7                      = 0x7,
3930 } SCL_HF_SHARP_SCALE_FACTOR;
3931 typedef enum SCL_HF_SHARP_EN {
3932 	SCL_HF_SHARP_DISABLE                             = 0x0,
3933 	SCL_HF_SHARP_ENABLE                              = 0x1,
3934 } SCL_HF_SHARP_EN;
3935 typedef enum SCL_VF_SHARP_SCALE_FACTOR {
3936 	SCL_VF_SHARP_SCALE_FACTOR_0                      = 0x0,
3937 	SCL_VF_SHARP_SCALE_FACTOR_1                      = 0x1,
3938 	SCL_VF_SHARP_SCALE_FACTOR_2                      = 0x2,
3939 	SCL_VF_SHARP_SCALE_FACTOR_3                      = 0x3,
3940 	SCL_VF_SHARP_SCALE_FACTOR_4                      = 0x4,
3941 	SCL_VF_SHARP_SCALE_FACTOR_5                      = 0x5,
3942 	SCL_VF_SHARP_SCALE_FACTOR_6                      = 0x6,
3943 	SCL_VF_SHARP_SCALE_FACTOR_7                      = 0x7,
3944 } SCL_VF_SHARP_SCALE_FACTOR;
3945 typedef enum SCL_VF_SHARP_EN {
3946 	SCL_VF_SHARP_DISABLE                             = 0x0,
3947 	SCL_VF_SHARP_ENABLE                              = 0x1,
3948 } SCL_VF_SHARP_EN;
3949 typedef enum SCL_ALU_DISABLE {
3950 	SCL_ALU_ENABLED                                  = 0x0,
3951 	SCL_ALU_DISABLED                                 = 0x1,
3952 } SCL_ALU_DISABLE;
3953 typedef enum SCL_HOST_CONFLICT_MASK {
3954 	SCL_HOST_CONFLICT_DISABLE_INTERRUPT              = 0x0,
3955 	SCL_HOST_CONFLICT_ENABLE_INTERRUPT               = 0x1,
3956 } SCL_HOST_CONFLICT_MASK;
3957 typedef enum SCL_SCL_MODE_CHANGE_MASK {
3958 	SCL_MODE_CHANGE_DISABLE_INTERRUPT                = 0x0,
3959 	SCL_MODE_CHANGE_ENABLE_INTERRUPT                 = 0x1,
3960 } SCL_SCL_MODE_CHANGE_MASK;
3961 typedef enum SCLV_MODE_SEL {
3962 	SCLV_MODE_RGB_BYPASS                             = 0x0,
3963 	SCLV_MODE_RGB_SCALING                            = 0x1,
3964 	SCLV_MODE_YCBCR_SCALING                          = 0x2,
3965 	SCLV_MODE_YCBCR_BYPASS                           = 0x3,
3966 } SCLV_MODE_SEL;
3967 typedef enum SCLV_INTERLACE_SOURCE {
3968 	INTERLACE_SOURCE_PROGRESSIVE                     = 0x0,
3969 	INTERLACE_SOURCE_INTERLEAVE                      = 0x1,
3970 	INTERLACE_SOURCE_STACK                           = 0x2,
3971 } SCLV_INTERLACE_SOURCE;
3972 typedef enum SCLV_UPDATE_LOCK {
3973 	UPDATE_UNLOCKED                                  = 0x0,
3974 	UPDATE_LOCKED                                    = 0x1,
3975 } SCLV_UPDATE_LOCK;
3976 typedef enum SCLV_COEF_UPDATE_COMPLETE {
3977 	COEF_UPDATE_NOT_COMPLETE                         = 0x0,
3978 	COEF_UPDATE_COMPLETE                             = 0x1,
3979 } SCLV_COEF_UPDATE_COMPLETE;
3980 typedef enum COL_MAN_UPDATE_LOCK {
3981 	COL_MAN_UPDATE_UNLOCKED                          = 0x0,
3982 	COL_MAN_UPDATE_LOCKED                            = 0x1,
3983 } COL_MAN_UPDATE_LOCK;
3984 typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE {
3985 	COL_MAN_MULTIPLE_UPDATE                          = 0x0,
3986 	COL_MAN_MULTIPLE_UPDAT_EDISABLE                  = 0x1,
3987 } COL_MAN_DISABLE_MULTIPLE_UPDATE;
3988 typedef enum COL_MAN_INPUTCSC_MODE {
3989 	INPUTCSC_MODE_BYPASS                             = 0x0,
3990 	INPUTCSC_MODE_A                                  = 0x1,
3991 	INPUTCSC_MODE_B                                  = 0x2,
3992 	INPUTCSC_MODE_UNITY                              = 0x3,
3993 } COL_MAN_INPUTCSC_MODE;
3994 typedef enum COL_MAN_INPUTCSC_TYPE {
3995 	INPUTCSC_TYPE_12_0                               = 0x0,
3996 	INPUTCSC_TYPE_10_2                               = 0x1,
3997 	INPUTCSC_TYPE_8_4                                = 0x2,
3998 } COL_MAN_INPUTCSC_TYPE;
3999 typedef enum COL_MAN_INPUTCSC_CONVERT {
4000 	INPUTCSC_ROUND                                   = 0x0,
4001 	INPUTCSC_TRUNCATE                                = 0x1,
4002 } COL_MAN_INPUTCSC_CONVERT;
4003 typedef enum COL_MAN_PRESCALE_MODE {
4004 	PRESCALE_MODE_BYPASS                             = 0x0,
4005 	PRESCALE_MODE_PROGRAM                            = 0x1,
4006 	PRESCALE_MODE_UNITY                              = 0x2,
4007 } COL_MAN_PRESCALE_MODE;
4008 typedef enum COL_MAN_INPUT_GAMMA_MODE {
4009 	INGAMMA_MODE_BYPASS                              = 0x0,
4010 	INGAMMA_MODE_FIX                                 = 0x1,
4011 	INGAMMA_MODE_FLOAT                               = 0x2,
4012 } COL_MAN_INPUT_GAMMA_MODE;
4013 typedef enum COL_MAN_OUTPUT_CSC_MODE {
4014 	COL_MAN_OUTPUT_CSC_BYPASS                        = 0x0,
4015 	COL_MAN_OUTPUT_CSC_RGB                           = 0x1,
4016 	COL_MAN_OUTPUT_CSC_YCrCb601                      = 0x2,
4017 	COL_MAN_OUTPUT_CSC_YCrCb709                      = 0x3,
4018 	COL_MAN_OUTPUT_CSC_A                             = 0x4,
4019 	COL_MAN_OUTPUT_CSC_B                             = 0x5,
4020 	COL_MAN_OUTPUT_CSC_UNITY                         = 0x6,
4021 } COL_MAN_OUTPUT_CSC_MODE;
4022 typedef enum COL_MAN_DENORM_CLAMP_CONTROL {
4023 	DENORM_CLAMP_MODE_UNITY                          = 0x0,
4024 	DENORM_CLAMP_MODE_8                              = 0x1,
4025 	DENORM_CLAMP_MODE_10                             = 0x2,
4026 	DENORM_CLAMP_MODE_12                             = 0x3,
4027 } COL_MAN_DENORM_CLAMP_CONTROL;
4028 typedef enum COL_MAN_GAMMA_CORR_CONTROL {
4029 	GAMMA_CORR_MODE_BYPASS                           = 0x0,
4030 	GAMMA_CORR_MODE_A                                = 0x1,
4031 	GAMMA_CORR_MODE_B                                = 0x2,
4032 } COL_MAN_GAMMA_CORR_CONTROL;
4033 typedef enum COL_MAN_GLOBAL_PASSTHROUGH_ENABLE {
4034 	CM_GLOBAL_PASSTHROUGH_DISBALE                    = 0x0,
4035 	CM_GLOBAL_PASSTHROUGH_ENABLE                     = 0x1,
4036 } COL_MAN_GLOBAL_PASSTHROUGH_ENABLE;
4037 typedef enum UNP_GRPH_EN {
4038 	UNP_GRPH_DISABLED                                = 0x0,
4039 	UNP_GRPH_ENABLED                                 = 0x1,
4040 } UNP_GRPH_EN;
4041 typedef enum UNP_GRPH_DEPTH {
4042 	UNP_GRPH_8BPP                                    = 0x0,
4043 	UNP_GRPH_16BPP                                   = 0x1,
4044 	UNP_GRPH_32BPP                                   = 0x2,
4045 } UNP_GRPH_DEPTH;
4046 typedef enum UNP_GRPH_NUM_BANKS {
4047 	UNP_GRPH_ADDR_SURF_2_BANK                        = 0x0,
4048 	UNP_GRPH_ADDR_SURF_4_BANK                        = 0x1,
4049 	UNP_GRPH_ADDR_SURF_8_BANK                        = 0x2,
4050 	UNP_GRPH_ADDR_SURF_16_BANK                       = 0x3,
4051 } UNP_GRPH_NUM_BANKS;
4052 typedef enum UNP_GRPH_BANK_WIDTH {
4053 	UNP_GRPH_ADDR_SURF_BANK_WIDTH_1                  = 0x0,
4054 	UNP_GRPH_ADDR_SURF_BANK_WIDTH_2                  = 0x1,
4055 	UNP_GRPH_ADDR_SURF_BANK_WIDTH_4                  = 0x2,
4056 	UNP_GRPH_ADDR_SURF_BANK_WIDTH_8                  = 0x3,
4057 } UNP_GRPH_BANK_WIDTH;
4058 typedef enum UNP_GRPH_BANK_HEIGHT {
4059 	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1                 = 0x0,
4060 	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2                 = 0x1,
4061 	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4                 = 0x2,
4062 	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8                 = 0x3,
4063 } UNP_GRPH_BANK_HEIGHT;
4064 typedef enum UNP_GRPH_TILE_SPLIT {
4065 	UNP_ADDR_SURF_TILE_SPLIT_64B                     = 0x0,
4066 	UNP_ADDR_SURF_TILE_SPLIT_128B                    = 0x1,
4067 	UNP_ADDR_SURF_TILE_SPLIT_256B                    = 0x2,
4068 	UNP_ADDR_SURF_TILE_SPLIT_512B                    = 0x3,
4069 	UNP_ADDR_SURF_TILE_SPLIT_1KB                     = 0x4,
4070 	UNP_ADDR_SURF_TILE_SPLIT_2KB                     = 0x5,
4071 	UNP_ADDR_SURF_TILE_SPLIT_4KB                     = 0x6,
4072 } UNP_GRPH_TILE_SPLIT;
4073 typedef enum UNP_GRPH_ADDRESS_TRANSLATION_ENABLE {
4074 	UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0             = 0x0,
4075 	UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1             = 0x1,
4076 } UNP_GRPH_ADDRESS_TRANSLATION_ENABLE;
4077 typedef enum UNP_GRPH_PRIVILEGED_ACCESS_ENABLE {
4078 	UNP_GRPH_PRIVILEGED_ACCESS_DIS                   = 0x0,
4079 	UNP_GRPH_PRIVILEGED_ACCESS_EN                    = 0x1,
4080 } UNP_GRPH_PRIVILEGED_ACCESS_ENABLE;
4081 typedef enum UNP_GRPH_MACRO_TILE_ASPECT {
4082 	UNP_ADDR_SURF_MACRO_ASPECT_1                     = 0x0,
4083 	UNP_ADDR_SURF_MACRO_ASPECT_2                     = 0x1,
4084 	UNP_ADDR_SURF_MACRO_ASPECT_4                     = 0x2,
4085 	UNP_ADDR_SURF_MACRO_ASPECT_8                     = 0x3,
4086 } UNP_GRPH_MACRO_TILE_ASPECT;
4087 typedef enum UNP_GRPH_COLOR_EXPANSION_MODE {
4088 	UNP_GRPH_DYNAMIC_EXPANSION                       = 0x0,
4089 	UNP_GRPH_ZERO_EXPANSION                          = 0x1,
4090 } UNP_GRPH_COLOR_EXPANSION_MODE;
4091 typedef enum UNP_VIDEO_FORMAT {
4092 	UNP_VIDEO_FORMAT0                                = 0x0,
4093 	UNP_VIDEO_FORMAT1                                = 0x1,
4094 	UNP_VIDEO_FORMAT_YUV420_YCbCr                    = 0x2,
4095 	UNP_VIDEO_FORMAT_YUV420_YCrCb                    = 0x3,
4096 	UNP_VIDEO_FORMAT_YUV422_YCb                      = 0x4,
4097 	UNP_VIDEO_FORMAT_YUV422_YCr                      = 0x5,
4098 	UNP_VIDEO_FORMAT_YUV422_CbY                      = 0x6,
4099 	UNP_VIDEO_FORMAT_YUV422_CrY                      = 0x7,
4100 } UNP_VIDEO_FORMAT;
4101 typedef enum UNP_GRPH_ENDIAN_SWAP {
4102 	UNP_GRPH_ENDIAN_SWAP_NONE                        = 0x0,
4103 	UNP_GRPH_ENDIAN_SWAP_8IN16                       = 0x1,
4104 	UNP_GRPH_ENDIAN_SWAP_8IN32                       = 0x2,
4105 	UNP_GRPH_ENDIAN_SWAP_8IN43                       = 0x3,
4106 } UNP_GRPH_ENDIAN_SWAP;
4107 typedef enum UNP_GRPH_RED_CROSSBAR {
4108 	UNP_GRPH_RED_CROSSBAR_R_Cr                       = 0x0,
4109 	UNP_GRPH_RED_CROSSBAR_G_Y                        = 0x1,
4110 	UNP_GRPH_RED_CROSSBAR_B_Cb                       = 0x2,
4111 	UNP_GRPH_RED_CROSSBAR_A                          = 0x3,
4112 } UNP_GRPH_RED_CROSSBAR;
4113 typedef enum UNP_GRPH_GREEN_CROSSBAR {
4114 	UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y             = 0x0,
4115 	UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C           = 0x1,
4116 	UNP_UNP_GRPH_GREEN_CROSSBAR_A                    = 0x2,
4117 	UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr                 = 0x3,
4118 } UNP_GRPH_GREEN_CROSSBAR;
4119 typedef enum UNP_GRPH_BLUE_CROSSBAR {
4120 	UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C                = 0x0,
4121 	UNP_GRPH_BLUE_CROSSBAR_A                         = 0x1,
4122 	UNP_GRPH_BLUE_CROSSBAR_R_Cr                      = 0x2,
4123 	UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y                  = 0x3,
4124 } UNP_GRPH_BLUE_CROSSBAR;
4125 typedef enum UNP_GRPH_MODE_UPDATE_LOCKG {
4126 	UNP_GRPH_UPDATE_LOCK_0                           = 0x0,
4127 	UNP_GRPH_UPDATE_LOCK_1                           = 0x1,
4128 } UNP_GRPH_MODE_UPDATE_LOCKG;
4129 typedef enum UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
4130 	UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0            = 0x0,
4131 	UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1            = 0x1,
4132 } UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
4133 typedef enum UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
4134 	UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0          = 0x0,
4135 	UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1          = 0x1,
4136 } UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
4137 typedef enum UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
4138 	UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0       = 0x0,
4139 	UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1       = 0x1,
4140 } UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
4141 typedef enum UNP_GRPH_STEREOSYNC_FLIP_EN {
4142 	UNP_GRPH_STEREOSYNC_FLIP_DISABLE                 = 0x0,
4143 	UNP_GRPH_STEREOSYNC_FLIP_ENABLE                  = 0x1,
4144 } UNP_GRPH_STEREOSYNC_FLIP_EN;
4145 typedef enum UNP_GRPH_STEREOSYNC_FLIP_MODE {
4146 	UNP_GRPH_STEREOSYNC_FLIP_MODE_0                  = 0x0,
4147 	UNP_GRPH_STEREOSYNC_FLIP_MODE_1                  = 0x1,
4148 	UNP_GRPH_STEREOSYNC_FLIP_MODE_2                  = 0x2,
4149 	UNP_GRPH_STEREOSYNC_FLIP_MODE_3                  = 0x3,
4150 } UNP_GRPH_STEREOSYNC_FLIP_MODE;
4151 typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_EN {
4152 	UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE            = 0x0,
4153 	UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE             = 0x1,
4154 } UNP_GRPH_STACK_INTERLACE_FLIP_EN;
4155 typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_MODE {
4156 	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0             = 0x0,
4157 	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1             = 0x1,
4158 	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2             = 0x2,
4159 	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3             = 0x3,
4160 } UNP_GRPH_STACK_INTERLACE_FLIP_MODE;
4161 typedef enum UNP_GRPH_STEREOSYNC_SELECT_DISABLE {
4162 	UNP_GRPH_STEREOSYNC_SELECT_EN                    = 0x0,
4163 	UNP_GRPH_STEREOSYNC_SELECT_DIS                   = 0x1,
4164 } UNP_GRPH_STEREOSYNC_SELECT_DISABLE;
4165 typedef enum UNP_CRC_SOURCE_SEL {
4166 	UNP_CRC_SOURCE_SEL_NP_TO_LBV                     = 0x0,
4167 	UNP_CRC_SOURCE_SEL_LOWER32                       = 0x1,
4168 	UNP_CRC_SOURCE_SEL_RESERVED                      = 0x2,
4169 	UNP_CRC_SOURCE_SEL_LOWER16                       = 0x3,
4170 	UNP_CRC_SOURCE_SEL_UNP_TO_LBV                    = 0x4,
4171 } UNP_CRC_SOURCE_SEL;
4172 typedef enum UNP_CRC_LINE_SEL {
4173 	UNP_CRC_LINE_SEL_RESERVED                        = 0x0,
4174 	UNP_CRC_LINE_SEL_EVEN_ONLY                       = 0x1,
4175 	UNP_CRC_LINE_SEL_ODD_ONLY                        = 0x2,
4176 	UNP_CRC_LINE_SEL_ODD_EVEN                        = 0x3,
4177 } UNP_CRC_LINE_SEL;
4178 typedef enum UNP_ROTATION_ANGLE {
4179 	UNP_ROTATION_ANGLE_0                             = 0x0,
4180 	UNP_ROTATION_ANGLE_90                            = 0x1,
4181 	UNP_ROTATION_ANGLE_180                           = 0x2,
4182 	UNP_ROTATION_ANGLE_270                           = 0x3,
4183 	UNP_ROTATION_ANGLE_0m                            = 0x4,
4184 	UNP_ROTATION_ANGLE_90m                           = 0x5,
4185 	UNP_ROTATION_ANGLE_180m                          = 0x6,
4186 	UNP_ROTATION_ANGLE_270m                          = 0x7,
4187 } UNP_ROTATION_ANGLE;
4188 typedef enum UNP_PIXEL_DROP {
4189 	UNP_PIXEL_NO_DROP                                = 0x0,
4190 	UNP_PIXEL_DROPPING                               = 0x1,
4191 } UNP_PIXEL_DROP;
4192 typedef enum UNP_BUFFER_MODE {
4193 	UNP_BUFFER_MODE_LUMA                             = 0x0,
4194 	UNP_BUFFER_MODE_LUMA_CHROMA                      = 0x1,
4195 } UNP_BUFFER_MODE;
4196 typedef enum WATERMARK_MASK_CONTROL {
4197 	WM_MASK_CONTROL_SET_A                            = 0x0,
4198 	WM_MASK_CONTROL_SET_B                            = 0x1,
4199 	WM_MASK_CONTROL_SET_C                            = 0x2,
4200 	WM_MASK_CONTROL_SET_D                            = 0x3,
4201 	WM_MASK_CONTROL_RESERVED1                        = 0x4,
4202 	WM_MASK_CONTROL_RESERVED2                        = 0x5,
4203 	WM_MASK_CONTROL_RESERVED3                        = 0x6,
4204 	WM_MASK_CONTROL_ACTIVE_SET                       = 0x7,
4205 } WATERMARK_MASK_CONTROL;
4206 typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
4207 	AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET= 0x0,
4208 	AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET= 0x1,
4209 } AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET;
4210 typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
4211 	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL= 0x0,
4212 	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6= 0x1,
4213 	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5= 0x2,
4214 	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4= 0x3,
4215 	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3= 0x4,
4216 	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2= 0x5,
4217 	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1= 0x6,
4218 	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0= 0x7,
4219 } CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY;
4220 typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
4221 	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL= 0x0,
4222 	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6= 0x1,
4223 	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5= 0x2,
4224 	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4= 0x3,
4225 	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3= 0x4,
4226 	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2= 0x5,
4227 	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1= 0x6,
4228 	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0= 0x7,
4229 } CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY;
4230 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
4231 	GENERIC_AZ_CONTROLLER_REGISTER_DISABLE           = 0x0,
4232 	GENERIC_AZ_CONTROLLER_REGISTER_ENABLE            = 0x1,
4233 } GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL;
4234 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
4235 	GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED  = 0x0,
4236 	GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED   = 0x1,
4237 } GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED;
4238 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
4239 	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET    = 0x0,
4240 	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET        = 0x1,
4241 } GENERIC_AZ_CONTROLLER_REGISTER_STATUS;
4242 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
4243 	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED= 0x0,
4244 	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED= 0x1,
4245 } GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED;
4246 typedef enum AZ_GLOBAL_CAPABILITIES {
4247 	AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED= 0x0,
4248 	AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED= 0x1,
4249 } AZ_GLOBAL_CAPABILITIES;
4250 typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
4251 	ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE           = 0x0,
4252 	ACCEPT_UNSOLICITED_RESPONSE_ENABLE               = 0x1,
4253 } GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE;
4254 typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
4255 	FLUSH_CONTROL_FLUSH_NOT_STARTED                  = 0x0,
4256 	FLUSH_CONTROL_FLUSH_STARTED                      = 0x1,
4257 } GLOBAL_CONTROL_FLUSH_CONTROL;
4258 typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
4259 	CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET          = 0x0,
4260 	CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET      = 0x1,
4261 } GLOBAL_CONTROL_CONTROLLER_RESET;
4262 typedef enum AZ_STATE_CHANGE_STATUS {
4263 	AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT         = 0x0,
4264 	AZ_STATE_CHANGE_STATUS_CODEC_PRESENT             = 0x1,
4265 } AZ_STATE_CHANGE_STATUS;
4266 typedef enum GLOBAL_STATUS_FLUSH_STATUS {
4267 	GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED       = 0x0,
4268 	GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED           = 0x1,
4269 } GLOBAL_STATUS_FLUSH_STATUS;
4270 typedef enum STREAM_0_SYNCHRONIZATION {
4271 	STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED       = 0x0,
4272 	STREAM_0_SYNCHRONIZATION_STEAM_STOPPED           = 0x1,
4273 } STREAM_0_SYNCHRONIZATION;
4274 typedef enum STREAM_1_SYNCHRONIZATION {
4275 	STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED       = 0x0,
4276 	STREAM_1_SYNCHRONIZATION_STEAM_STOPPED           = 0x1,
4277 } STREAM_1_SYNCHRONIZATION;
4278 typedef enum STREAM_2_SYNCHRONIZATION {
4279 	STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED       = 0x0,
4280 	STREAM_2_SYNCHRONIZATION_STEAM_STOPPED           = 0x1,
4281 } STREAM_2_SYNCHRONIZATION;
4282 typedef enum STREAM_3_SYNCHRONIZATION {
4283 	STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED       = 0x0,
4284 	STREAM_3_SYNCHRONIZATION_STEAM_STOPPED           = 0x1,
4285 } STREAM_3_SYNCHRONIZATION;
4286 typedef enum STREAM_4_SYNCHRONIZATION {
4287 	STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED       = 0x0,
4288 	STREAM_4_SYNCHRONIZATION_STEAM_STOPPED           = 0x1,
4289 } STREAM_4_SYNCHRONIZATION;
4290 typedef enum STREAM_5_SYNCHRONIZATION {
4291 	STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED       = 0x0,
4292 	STREAM_5_SYNCHRONIZATION_STEAM_STOPPED           = 0x1,
4293 } STREAM_5_SYNCHRONIZATION;
4294 typedef enum STREAM_6_SYNCHRONIZATION {
4295 	STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
4296 	STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x1,
4297 } STREAM_6_SYNCHRONIZATION;
4298 typedef enum STREAM_7_SYNCHRONIZATION {
4299 	STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
4300 	STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x1,
4301 } STREAM_7_SYNCHRONIZATION;
4302 typedef enum STREAM_8_SYNCHRONIZATION {
4303 	STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
4304 	STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x1,
4305 } STREAM_8_SYNCHRONIZATION;
4306 typedef enum STREAM_9_SYNCHRONIZATION {
4307 	STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
4308 	STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x1,
4309 } STREAM_9_SYNCHRONIZATION;
4310 typedef enum STREAM_10_SYNCHRONIZATION {
4311 	STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
4312 	STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
4313 } STREAM_10_SYNCHRONIZATION;
4314 typedef enum STREAM_11_SYNCHRONIZATION {
4315 	STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
4316 	STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
4317 } STREAM_11_SYNCHRONIZATION;
4318 typedef enum STREAM_12_SYNCHRONIZATION {
4319 	STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
4320 	STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
4321 } STREAM_12_SYNCHRONIZATION;
4322 typedef enum STREAM_13_SYNCHRONIZATION {
4323 	STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
4324 	STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
4325 } STREAM_13_SYNCHRONIZATION;
4326 typedef enum STREAM_14_SYNCHRONIZATION {
4327 	STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
4328 	STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
4329 } STREAM_14_SYNCHRONIZATION;
4330 typedef enum STREAM_15_SYNCHRONIZATION {
4331 	STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
4332 	STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
4333 } STREAM_15_SYNCHRONIZATION;
4334 typedef enum CORB_READ_POINTER_RESET {
4335 	CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET    = 0x0,
4336 	CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET        = 0x1,
4337 } CORB_READ_POINTER_RESET;
4338 typedef enum AZ_CORB_SIZE {
4339 	AZ_CORB_SIZE_2ENTRIES_RESERVED                   = 0x0,
4340 	AZ_CORB_SIZE_16ENTRIES_RESERVED                  = 0x1,
4341 	AZ_CORB_SIZE_256ENTRIES                          = 0x2,
4342 	AZ_CORB_SIZE_RESERVED                            = 0x3,
4343 } AZ_CORB_SIZE;
4344 typedef enum AZ_RIRB_WRITE_POINTER_RESET {
4345 	AZ_RIRB_WRITE_POINTER_NOT_RESET                  = 0x0,
4346 	AZ_RIRB_WRITE_POINTER_DO_RESET                   = 0x1,
4347 } AZ_RIRB_WRITE_POINTER_RESET;
4348 typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
4349 	RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED= 0x0,
4350 	RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED= 0x1,
4351 } RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL;
4352 typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
4353 	RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED= 0x0,
4354 	RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED= 0x1,
4355 } RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL;
4356 typedef enum AZ_RIRB_SIZE {
4357 	AZ_RIRB_SIZE_2ENTRIES_RESERVED                   = 0x0,
4358 	AZ_RIRB_SIZE_16ENTRIES_RESERVED                  = 0x1,
4359 	AZ_RIRB_SIZE_256ENTRIES                          = 0x2,
4360 	AZ_RIRB_SIZE_UNDEFINED                           = 0x3,
4361 } AZ_RIRB_SIZE;
4362 typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
4363 	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID= 0x0,
4364 	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID= 0x1,
4365 } IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID;
4366 typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
4367 	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY= 0x0,
4368 	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY= 0x1,
4369 } IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY;
4370 typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
4371 	DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE= 0x0,
4372 	DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE= 0x1,
4373 } DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE;
4374 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
4375 	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET= 0x0,
4376 	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET= 0x1,
4377 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR;
4378 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
4379 	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET= 0x0,
4380 	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET= 0x1,
4381 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR;
4382 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
4383 	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET= 0x0,
4384 	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET= 0x1,
4385 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS;
4386 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
4387 	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY= 0x0,
4388 	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY= 0x1,
4389 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY;
4390 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
4391 	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED= 0x0,
4392 	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED= 0x1,
4393 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE;
4394 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
4395 	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED= 0x0,
4396 	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED= 0x1,
4397 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE;
4398 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
4399 	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED= 0x0,
4400 	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED= 0x1,
4401 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE;
4402 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
4403 	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN= 0x0,
4404 	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN= 0x1,
4405 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN;
4406 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
4407 	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET= 0x0,
4408 	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET= 0x1,
4409 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET;
4410 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
4411 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0,
4412 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1,
4413 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE;
4414 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
4415 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0,
4416 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1,
4417 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
4418 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3,
4419 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4,
4420 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE;
4421 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
4422 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0,
4423 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1,
4424 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
4425 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3,
4426 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4,
4427 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5,
4428 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6,
4429 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7,
4430 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR;
4431 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
4432 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0,
4433 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16= 0x1,
4434 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20= 0x2,
4435 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24= 0x3,
4436 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4,
4437 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5,
4438 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE;
4439 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
4440 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1= 0x0,
4441 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2= 0x1,
4442 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
4443 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4= 0x3,
4444 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5= 0x4,
4445 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6= 0x5,
4446 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7= 0x6,
4447 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8= 0x7,
4448 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED= 0x8,
4449 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED= 0x9,
4450 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED= 0xa,
4451 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED= 0xb,
4452 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED= 0xc,
4453 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED= 0xd,
4454 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED= 0xe,
4455 	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED= 0xf,
4456 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS;
4457 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
4458 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM= 0x0,
4459 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM= 0x1,
4460 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
4461 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
4462 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0,
4463 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1,
4464 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
4465 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
4466 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0,
4467 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1,
4468 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
4469 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3,
4470 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4,
4471 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
4472 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
4473 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0,
4474 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1,
4475 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
4476 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3,
4477 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4,
4478 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5,
4479 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6,
4480 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7,
4481 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
4482 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
4483 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0,
4484 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16= 0x1,
4485 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2,
4486 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24= 0x3,
4487 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4,
4488 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5,
4489 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
4490 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
4491 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1= 0x0,
4492 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2= 0x1,
4493 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
4494 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4= 0x3,
4495 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5= 0x4,
4496 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6= 0x5,
4497 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7= 0x6,
4498 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8= 0x7,
4499 	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED= 0x8,
4500 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
4501 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
4502 	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET= 0x0,
4503 	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET= 0x1,
4504 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L;
4505 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
4506 	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET= 0x0,
4507 	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET= 0x1,
4508 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO;
4509 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
4510 	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET= 0x0,
4511 	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET= 0x1,
4512 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO;
4513 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
4514 	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET= 0x0,
4515 	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET= 0x1,
4516 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY;
4517 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
4518 	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET= 0x0,
4519 	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET= 0x1,
4520 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE;
4521 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
4522 	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON= 0x0,
4523 	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON= 0x1,
4524 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG;
4525 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
4526 	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO= 0x0,
4527 	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE= 0x1,
4528 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V;
4529 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
4530 	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED= 0x0,
4531 	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED= 0x1,
4532 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
4533 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
4534 	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE= 0x0,
4535 	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE= 0x1,
4536 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE;
4537 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
4538 	AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF= 0x0,
4539 	AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN= 0x1,
4540 } AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE;
4541 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
4542 	AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED= 0x0,
4543 	AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED= 0x1,
4544 } AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
4545 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
4546 	AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED= 0x0,
4547 	AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN   = 0x1,
4548 } AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT;
4549 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
4550 	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED= 0x0,
4551 	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED= 0x1,
4552 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE;
4553 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
4554 	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED= 0x0,
4555 	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED= 0x1,
4556 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE;
4557 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
4558 	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED= 0x0,
4559 	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED= 0x1,
4560 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE;
4561 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
4562 	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED= 0x0,
4563 	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED= 0x1,
4564 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE;
4565 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
4566 	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED= 0x0,
4567 	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED= 0x1,
4568 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
4569 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
4570 	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED= 0x0,
4571 	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED= 0x1,
4572 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
4573 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
4574 	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED= 0x0,
4575 	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED= 0x1,
4576 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
4577 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
4578 	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED= 0x0,
4579 	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED= 0x1,
4580 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
4581 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
4582 	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE= 0x0,
4583 	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE= 0x1,
4584 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
4585 typedef enum AZ_LATENCY_COUNTER_CONTROL {
4586 	AZ_LATENCY_COUNTER_NO_RESET                      = 0x0,
4587 	AZ_LATENCY_COUNTER_RESET_DONE                    = 0x1,
4588 } AZ_LATENCY_COUNTER_CONTROL;
4589 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
4590 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
4591 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
4592 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
4593 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
4594 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
4595 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
4596 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
4597 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
4598 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED= 0x8,
4599 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
4600 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
4601 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
4602 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0,
4603 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1,
4604 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
4605 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
4606 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
4607 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
4608 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
4609 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
4610 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0,
4611 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1,
4612 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
4613 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
4614 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
4615 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
4616 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
4617 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
4618 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
4619 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
4620 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
4621 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
4622 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES= 0x0,
4623 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES= 0x1,
4624 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
4625 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
4626 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0,
4627 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
4628 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
4629 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
4630 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE= 0x0,
4631 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE= 0x1,
4632 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
4633 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
4634 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
4635 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1,
4636 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
4637 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
4638 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
4639 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
4640 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
4641 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
4642 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0,
4643 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
4644 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
4645 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
4646 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC= 0x0,
4647 	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO= 0x1,
4648 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
4649 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
4650 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
4651 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
4652 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
4653 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
4654 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
4655 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
4656 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
4657 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
4658 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED= 0x8,
4659 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
4660 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
4661 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
4662 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0,
4663 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1,
4664 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
4665 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
4666 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
4667 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
4668 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
4669 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
4670 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0,
4671 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1,
4672 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
4673 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
4674 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
4675 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
4676 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
4677 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
4678 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
4679 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
4680 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
4681 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
4682 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES= 0x0,
4683 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES= 0x1,
4684 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
4685 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
4686 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0,
4687 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
4688 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
4689 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
4690 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
4691 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1,
4692 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
4693 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
4694 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
4695 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
4696 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
4697 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
4698 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT= 0x0,
4699 	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
4700 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
4701 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
4702 	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN= 0x0,
4703 	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN= 0x1,
4704 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
4705 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
4706 	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED= 0x0,
4707 	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED= 0x1,
4708 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
4709 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
4710 	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN= 0x0,
4711 	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN= 0x1,
4712 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
4713 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
4714 	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN= 0x0,
4715 	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN= 0x1,
4716 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
4717 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
4718 	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY= 0x0,
4719 	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY= 0x1,
4720 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
4721 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
4722 	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY= 0x0,
4723 	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY= 0x1,
4724 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
4725 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
4726 	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x0,
4727 	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x1,
4728 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
4729 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
4730 	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY= 0x0,
4731 	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY= 0x1,
4732 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
4733 typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
4734 	AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE= 0x0,
4735 	AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE= 0x1,
4736 } AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
4737 typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
4738 	AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY= 0x0,
4739 	AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY= 0x1,
4740 } AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
4741 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
4742 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
4743 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
4744 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
4745 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
4746 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
4747 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
4748 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
4749 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
4750 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED= 0x8,
4751 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
4752 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
4753 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
4754 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0,
4755 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1,
4756 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
4757 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
4758 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
4759 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
4760 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
4761 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
4762 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG= 0x0,
4763 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL= 0x1,
4764 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
4765 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
4766 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
4767 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
4768 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
4769 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
4770 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
4771 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
4772 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
4773 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
4774 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES= 0x0,
4775 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES= 0x1,
4776 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
4777 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
4778 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING= 0x0,
4779 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
4780 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
4781 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
4782 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE= 0x0,
4783 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE= 0x1,
4784 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
4785 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
4786 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
4787 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER= 0x1,
4788 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
4789 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
4790 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
4791 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
4792 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
4793 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
4794 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0,
4795 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
4796 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
4797 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
4798 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC= 0x0,
4799 	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO= 0x1,
4800 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
4801 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
4802 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
4803 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
4804 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
4805 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
4806 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
4807 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
4808 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
4809 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
4810 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED= 0x8,
4811 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
4812 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
4813 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
4814 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP= 0x0,
4815 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP= 0x1,
4816 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
4817 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
4818 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
4819 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
4820 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
4821 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
4822 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0,
4823 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1,
4824 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
4825 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
4826 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
4827 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
4828 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
4829 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
4830 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
4831 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
4832 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
4833 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
4834 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES= 0x0,
4835 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES= 0x1,
4836 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
4837 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
4838 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0,
4839 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
4840 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
4841 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
4842 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
4843 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1,
4844 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
4845 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
4846 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
4847 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
4848 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
4849 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
4850 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0,
4851 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
4852 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
4853 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
4854 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED= 0x0,
4855 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED= 0x1,
4856 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP;
4857 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
4858 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN= 0x0,
4859 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN= 0x1,
4860 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
4861 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
4862 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED= 0x0,
4863 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED= 0x1,
4864 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI;
4865 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
4866 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED= 0x0,
4867 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED= 0x1,
4868 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
4869 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
4870 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN= 0x0,
4871 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN= 0x1,
4872 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
4873 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
4874 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN= 0x0,
4875 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN= 0x1,
4876 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
4877 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
4878 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY= 0x0,
4879 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY= 0x1,
4880 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
4881 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
4882 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY= 0x0,
4883 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY= 0x1,
4884 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
4885 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
4886 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x0,
4887 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x1,
4888 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
4889 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
4890 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY= 0x0,
4891 	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY= 0x1,
4892 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
4893 typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
4894 	AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY= 0x0,
4895 	AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY= 0x1,
4896 } AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
4897 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
4898 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM= 0x0,
4899 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM= 0x1,
4900 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
4901 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
4902 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0,
4903 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1,
4904 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
4905 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
4906 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0,
4907 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1,
4908 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
4909 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3,
4910 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4,
4911 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
4912 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
4913 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0,
4914 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1,
4915 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
4916 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3,
4917 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4,
4918 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5,
4919 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6,
4920 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7,
4921 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
4922 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
4923 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0,
4924 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16= 0x1,
4925 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2,
4926 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24= 0x3,
4927 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4,
4928 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5,
4929 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
4930 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
4931 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1= 0x0,
4932 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2= 0x1,
4933 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
4934 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4= 0x3,
4935 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5= 0x4,
4936 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6= 0x5,
4937 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7= 0x6,
4938 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8= 0x7,
4939 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED= 0x8,
4940 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
4941 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
4942 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED= 0x0,
4943 	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED= 0x1,
4944 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
4945 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
4946 	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF= 0x0,
4947 	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN= 0x1,
4948 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE;
4949 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
4950 	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED= 0x0,
4951 	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED= 0x1,
4952 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
4953 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
4954 	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED= 0x0,
4955 	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED= 0x1,
4956 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE;
4957 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
4958 	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED= 0x0,
4959 	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED= 0x1,
4960 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
4961 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
4962 	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED= 0x0,
4963 	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED= 0x1,
4964 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE;
4965 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
4966 	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED= 0x0,
4967 	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED= 0x1,
4968 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
4969 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
4970 	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED= 0x0,
4971 	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED= 0x1,
4972 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE;
4973 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
4974 	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED= 0x0,
4975 	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED= 0x1,
4976 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
4977 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
4978 	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED= 0x0,
4979 	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED= 0x1,
4980 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE;
4981 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
4982 	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED= 0x0,
4983 	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED= 0x1,
4984 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
4985 typedef enum BLND_CONTROL_BLND_MODE {
4986 	BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY         = 0x0,
4987 	BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY           = 0x1,
4988 	BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE       = 0x2,
4989 	BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE         = 0x3,
4990 } BLND_CONTROL_BLND_MODE;
4991 typedef enum BLND_CONTROL_BLND_STEREO_TYPE {
4992 	BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO= 0x0,
4993 	BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO= 0x1,
4994 	BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2,
4995 	BLND_CONTROL_BLND_STEREO_TYPE_UNUSED             = 0x3,
4996 } BLND_CONTROL_BLND_STEREO_TYPE;
4997 typedef enum BLND_CONTROL_BLND_STEREO_POLARITY {
4998 	BLND_CONTROL_BLND_STEREO_POLARITY_LOW            = 0x0,
4999 	BLND_CONTROL_BLND_STEREO_POLARITY_HIGH           = 0x1,
5000 } BLND_CONTROL_BLND_STEREO_POLARITY;
5001 typedef enum BLND_CONTROL_BLND_FEEDTHROUGH_EN {
5002 	BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE           = 0x0,
5003 	BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE            = 0x1,
5004 } BLND_CONTROL_BLND_FEEDTHROUGH_EN;
5005 typedef enum BLND_CONTROL_BLND_ALPHA_MODE {
5006 	BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x0,
5007 	BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN= 0x1,
5008 	BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY   = 0x2,
5009 	BLND_CONTROL_BLND_ALPHA_MODE_UNUSED              = 0x3,
5010 } BLND_CONTROL_BLND_ALPHA_MODE;
5011 typedef enum BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
5012 	BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE      = 0x0,
5013 	BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE       = 0x1,
5014 } BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY;
5015 typedef enum BLND_CONTROL_BLND_MULTIPLIED_MODE {
5016 	BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE          = 0x0,
5017 	BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE           = 0x1,
5018 } BLND_CONTROL_BLND_MULTIPLIED_MODE;
5019 typedef enum BLND_SM_CONTROL2_SM_MODE {
5020 	BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE            = 0x0,
5021 	BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING         = 0x2,
5022 	BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING      = 0x4,
5023 	BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING= 0x6,
5024 } BLND_SM_CONTROL2_SM_MODE;
5025 typedef enum BLND_SM_CONTROL2_SM_FRAME_ALTERNATE {
5026 	BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE        = 0x0,
5027 	BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE         = 0x1,
5028 } BLND_SM_CONTROL2_SM_FRAME_ALTERNATE;
5029 typedef enum BLND_SM_CONTROL2_SM_FIELD_ALTERNATE {
5030 	BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE        = 0x0,
5031 	BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE         = 0x1,
5032 } BLND_SM_CONTROL2_SM_FIELD_ALTERNATE;
5033 typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
5034 	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE= 0x0,
5035 	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED= 0x1,
5036 	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2,
5037 	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH= 0x3,
5038 } BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
5039 typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
5040 	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE  = 0x0,
5041 	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED  = 0x1,
5042 	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x2,
5043 	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH= 0x3,
5044 } BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
5045 typedef enum BLND_CONTROL2_PTI_ENABLE {
5046 	BLND_CONTROL2_PTI_ENABLE_FALSE                   = 0x0,
5047 	BLND_CONTROL2_PTI_ENABLE_TRUE                    = 0x1,
5048 } BLND_CONTROL2_PTI_ENABLE;
5049 typedef enum BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
5050 	BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE      = 0x0,
5051 	BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE       = 0x1,
5052 } BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
5053 typedef enum BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
5054 	BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE      = 0x0,
5055 	BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE       = 0x1,
5056 } BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
5057 typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
5058 	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE= 0x0,
5059 	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE= 0x1,
5060 } BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
5061 typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
5062 	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE= 0x0,
5063 	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE= 0x1,
5064 } BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
5065 typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
5066 	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE= 0x0,
5067 	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE= 0x1,
5068 } BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
5069 typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
5070 	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE= 0x0,
5071 	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE= 0x1,
5072 } BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
5073 typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
5074 	BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE= 0x0,
5075 	BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE= 0x1,
5076 } BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
5077 typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
5078 	BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE= 0x0,
5079 	BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE= 0x1,
5080 } BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
5081 typedef enum BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
5082 	BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE  = 0x0,
5083 	BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE   = 0x1,
5084 } BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
5085 typedef enum BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
5086 	BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x0,
5087 	BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE  = 0x1,
5088 } BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
5089 typedef enum BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
5090 	BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x0,
5091 	BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE  = 0x1,
5092 } BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
5093 typedef enum BLND_DEBUG_BLND_CNV_MUX_SELECT {
5094 	BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW               = 0x0,
5095 	BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH              = 0x1,
5096 } BLND_DEBUG_BLND_CNV_MUX_SELECT;
5097 typedef enum BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
5098 	BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE= 0x0,
5099 	BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE= 0x1,
5100 } BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
5101 typedef enum SurfaceEndian {
5102 	ENDIAN_NONE                                      = 0x0,
5103 	ENDIAN_8IN16                                     = 0x1,
5104 	ENDIAN_8IN32                                     = 0x2,
5105 	ENDIAN_8IN64                                     = 0x3,
5106 } SurfaceEndian;
5107 typedef enum ArrayMode {
5108 	ARRAY_LINEAR_GENERAL                             = 0x0,
5109 	ARRAY_LINEAR_ALIGNED                             = 0x1,
5110 	ARRAY_1D_TILED_THIN1                             = 0x2,
5111 	ARRAY_1D_TILED_THICK                             = 0x3,
5112 	ARRAY_2D_TILED_THIN1                             = 0x4,
5113 	ARRAY_PRT_TILED_THIN1                            = 0x5,
5114 	ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
5115 	ARRAY_2D_TILED_THICK                             = 0x7,
5116 	ARRAY_2D_TILED_XTHICK                            = 0x8,
5117 	ARRAY_PRT_TILED_THICK                            = 0x9,
5118 	ARRAY_PRT_2D_TILED_THICK                         = 0xa,
5119 	ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
5120 	ARRAY_3D_TILED_THIN1                             = 0xc,
5121 	ARRAY_3D_TILED_THICK                             = 0xd,
5122 	ARRAY_3D_TILED_XTHICK                            = 0xe,
5123 	ARRAY_PRT_3D_TILED_THICK                         = 0xf,
5124 } ArrayMode;
5125 typedef enum PipeTiling {
5126 	CONFIG_1_PIPE                                    = 0x0,
5127 	CONFIG_2_PIPE                                    = 0x1,
5128 	CONFIG_4_PIPE                                    = 0x2,
5129 	CONFIG_8_PIPE                                    = 0x3,
5130 } PipeTiling;
5131 typedef enum BankTiling {
5132 	CONFIG_4_BANK                                    = 0x0,
5133 	CONFIG_8_BANK                                    = 0x1,
5134 } BankTiling;
5135 typedef enum GroupInterleave {
5136 	CONFIG_256B_GROUP                                = 0x0,
5137 	CONFIG_512B_GROUP                                = 0x1,
5138 } GroupInterleave;
5139 typedef enum RowTiling {
5140 	CONFIG_1KB_ROW                                   = 0x0,
5141 	CONFIG_2KB_ROW                                   = 0x1,
5142 	CONFIG_4KB_ROW                                   = 0x2,
5143 	CONFIG_8KB_ROW                                   = 0x3,
5144 	CONFIG_1KB_ROW_OPT                               = 0x4,
5145 	CONFIG_2KB_ROW_OPT                               = 0x5,
5146 	CONFIG_4KB_ROW_OPT                               = 0x6,
5147 	CONFIG_8KB_ROW_OPT                               = 0x7,
5148 } RowTiling;
5149 typedef enum BankSwapBytes {
5150 	CONFIG_128B_SWAPS                                = 0x0,
5151 	CONFIG_256B_SWAPS                                = 0x1,
5152 	CONFIG_512B_SWAPS                                = 0x2,
5153 	CONFIG_1KB_SWAPS                                 = 0x3,
5154 } BankSwapBytes;
5155 typedef enum SampleSplitBytes {
5156 	CONFIG_1KB_SPLIT                                 = 0x0,
5157 	CONFIG_2KB_SPLIT                                 = 0x1,
5158 	CONFIG_4KB_SPLIT                                 = 0x2,
5159 	CONFIG_8KB_SPLIT                                 = 0x3,
5160 } SampleSplitBytes;
5161 typedef enum NumPipes {
5162 	ADDR_CONFIG_1_PIPE                               = 0x0,
5163 	ADDR_CONFIG_2_PIPE                               = 0x1,
5164 	ADDR_CONFIG_4_PIPE                               = 0x2,
5165 	ADDR_CONFIG_8_PIPE                               = 0x3,
5166 } NumPipes;
5167 typedef enum PipeInterleaveSize {
5168 	ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
5169 	ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
5170 } PipeInterleaveSize;
5171 typedef enum BankInterleaveSize {
5172 	ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
5173 	ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
5174 	ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
5175 	ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
5176 } BankInterleaveSize;
5177 typedef enum NumShaderEngines {
5178 	ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
5179 	ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
5180 } NumShaderEngines;
5181 typedef enum ShaderEngineTileSize {
5182 	ADDR_CONFIG_SE_TILE_16                           = 0x0,
5183 	ADDR_CONFIG_SE_TILE_32                           = 0x1,
5184 } ShaderEngineTileSize;
5185 typedef enum NumGPUs {
5186 	ADDR_CONFIG_1_GPU                                = 0x0,
5187 	ADDR_CONFIG_2_GPU                                = 0x1,
5188 	ADDR_CONFIG_4_GPU                                = 0x2,
5189 } NumGPUs;
5190 typedef enum MultiGPUTileSize {
5191 	ADDR_CONFIG_GPU_TILE_16                          = 0x0,
5192 	ADDR_CONFIG_GPU_TILE_32                          = 0x1,
5193 	ADDR_CONFIG_GPU_TILE_64                          = 0x2,
5194 	ADDR_CONFIG_GPU_TILE_128                         = 0x3,
5195 } MultiGPUTileSize;
5196 typedef enum RowSize {
5197 	ADDR_CONFIG_1KB_ROW                              = 0x0,
5198 	ADDR_CONFIG_2KB_ROW                              = 0x1,
5199 	ADDR_CONFIG_4KB_ROW                              = 0x2,
5200 } RowSize;
5201 typedef enum NumLowerPipes {
5202 	ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
5203 	ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
5204 } NumLowerPipes;
5205 typedef enum DebugBlockId {
5206 	DBG_CLIENT_BLKID_RESERVED                        = 0x0,
5207 	DBG_CLIENT_BLKID_dbg                             = 0x1,
5208 	DBG_CLIENT_BLKID_scf2                            = 0x2,
5209 	DBG_CLIENT_BLKID_mcd5                            = 0x3,
5210 	DBG_CLIENT_BLKID_vmc                             = 0x4,
5211 	DBG_CLIENT_BLKID_sx30                            = 0x5,
5212 	DBG_CLIENT_BLKID_mcd2                            = 0x6,
5213 	DBG_CLIENT_BLKID_bci1                            = 0x7,
5214 	DBG_CLIENT_BLKID_xdma_dbg_client_wrapper         = 0x8,
5215 	DBG_CLIENT_BLKID_mcc0                            = 0x9,
5216 	DBG_CLIENT_BLKID_uvdf_2                          = 0xa,
5217 	DBG_CLIENT_BLKID_uvdf_3                          = 0xb,
5218 	DBG_CLIENT_BLKID_uvdt_0                          = 0xc,
5219 	DBG_CLIENT_BLKID_uvdi_0                          = 0xd,
5220 	DBG_CLIENT_BLKID_bci0                            = 0xe,
5221 	DBG_CLIENT_BLKID_vceb0_1                         = 0xf,
5222 	DBG_CLIENT_BLKID_cb100                           = 0x10,
5223 	DBG_CLIENT_BLKID_cb001                           = 0x11,
5224 	DBG_CLIENT_BLKID_mcd4                            = 0x12,
5225 	DBG_CLIENT_BLKID_tmonw00                         = 0x13,
5226 	DBG_CLIENT_BLKID_cb101                           = 0x14,
5227 	DBG_CLIENT_BLKID_sx10                            = 0x15,
5228 	DBG_CLIENT_BLKID_cb301                           = 0x16,
5229 	DBG_CLIENT_BLKID_tmonw01                         = 0x17,
5230 	DBG_CLIENT_BLKID_vcea0_0                         = 0x18,
5231 	DBG_CLIENT_BLKID_vcea0_1                         = 0x19,
5232 	DBG_CLIENT_BLKID_vcea0_2                         = 0x1a,
5233 	DBG_CLIENT_BLKID_vcea0_3                         = 0x1b,
5234 	DBG_CLIENT_BLKID_scf1                            = 0x1c,
5235 	DBG_CLIENT_BLKID_sx20                            = 0x1d,
5236 	DBG_CLIENT_BLKID_spim1                           = 0x1e,
5237 	DBG_CLIENT_BLKID_pa10                            = 0x1f,
5238 	DBG_CLIENT_BLKID_pa00                            = 0x20,
5239 	DBG_CLIENT_BLKID_gmcon                           = 0x21,
5240 	DBG_CLIENT_BLKID_mcb                             = 0x22,
5241 	DBG_CLIENT_BLKID_vgt0                            = 0x23,
5242 	DBG_CLIENT_BLKID_pc0                             = 0x24,
5243 	DBG_CLIENT_BLKID_bci2                            = 0x25,
5244 	DBG_CLIENT_BLKID_uvdb_0                          = 0x26,
5245 	DBG_CLIENT_BLKID_spim3                           = 0x27,
5246 	DBG_CLIENT_BLKID_cpc_0                           = 0x28,
5247 	DBG_CLIENT_BLKID_cpc_1                           = 0x29,
5248 	DBG_CLIENT_BLKID_uvdm_0                          = 0x2a,
5249 	DBG_CLIENT_BLKID_uvdm_1                          = 0x2b,
5250 	DBG_CLIENT_BLKID_uvdm_2                          = 0x2c,
5251 	DBG_CLIENT_BLKID_uvdm_3                          = 0x2d,
5252 	DBG_CLIENT_BLKID_cb000                           = 0x2e,
5253 	DBG_CLIENT_BLKID_spim0                           = 0x2f,
5254 	DBG_CLIENT_BLKID_mcc2                            = 0x30,
5255 	DBG_CLIENT_BLKID_ds0                             = 0x31,
5256 	DBG_CLIENT_BLKID_srbm                            = 0x32,
5257 	DBG_CLIENT_BLKID_ih                              = 0x33,
5258 	DBG_CLIENT_BLKID_sem                             = 0x34,
5259 	DBG_CLIENT_BLKID_sdma_0                          = 0x35,
5260 	DBG_CLIENT_BLKID_sdma_1                          = 0x36,
5261 	DBG_CLIENT_BLKID_hdp                             = 0x37,
5262 	DBG_CLIENT_BLKID_cb200                           = 0x38,
5263 	DBG_CLIENT_BLKID_scf3                            = 0x39,
5264 	DBG_CLIENT_BLKID_vceb1_0                         = 0x3a,
5265 	DBG_CLIENT_BLKID_vcea1_0                         = 0x3b,
5266 	DBG_CLIENT_BLKID_vcea1_1                         = 0x3c,
5267 	DBG_CLIENT_BLKID_vcea1_2                         = 0x3d,
5268 	DBG_CLIENT_BLKID_vcea1_3                         = 0x3e,
5269 	DBG_CLIENT_BLKID_bci3                            = 0x3f,
5270 	DBG_CLIENT_BLKID_mcd0                            = 0x40,
5271 	DBG_CLIENT_BLKID_pa11                            = 0x41,
5272 	DBG_CLIENT_BLKID_pa01                            = 0x42,
5273 	DBG_CLIENT_BLKID_cb201                           = 0x43,
5274 	DBG_CLIENT_BLKID_spim2                           = 0x44,
5275 	DBG_CLIENT_BLKID_vgt2                            = 0x45,
5276 	DBG_CLIENT_BLKID_pc2                             = 0x46,
5277 	DBG_CLIENT_BLKID_smu_0                           = 0x47,
5278 	DBG_CLIENT_BLKID_smu_1                           = 0x48,
5279 	DBG_CLIENT_BLKID_smu_2                           = 0x49,
5280 	DBG_CLIENT_BLKID_cb1                             = 0x4a,
5281 	DBG_CLIENT_BLKID_ia0                             = 0x4b,
5282 	DBG_CLIENT_BLKID_wd                              = 0x4c,
5283 	DBG_CLIENT_BLKID_ia1                             = 0x4d,
5284 	DBG_CLIENT_BLKID_vcec1_0                         = 0x4e,
5285 	DBG_CLIENT_BLKID_scf0                            = 0x4f,
5286 	DBG_CLIENT_BLKID_vgt1                            = 0x50,
5287 	DBG_CLIENT_BLKID_pc1                             = 0x51,
5288 	DBG_CLIENT_BLKID_cb0                             = 0x52,
5289 	DBG_CLIENT_BLKID_gdc_one_0                       = 0x53,
5290 	DBG_CLIENT_BLKID_gdc_one_1                       = 0x54,
5291 	DBG_CLIENT_BLKID_gdc_one_2                       = 0x55,
5292 	DBG_CLIENT_BLKID_gdc_one_3                       = 0x56,
5293 	DBG_CLIENT_BLKID_gdc_one_4                       = 0x57,
5294 	DBG_CLIENT_BLKID_gdc_one_5                       = 0x58,
5295 	DBG_CLIENT_BLKID_gdc_one_6                       = 0x59,
5296 	DBG_CLIENT_BLKID_gdc_one_7                       = 0x5a,
5297 	DBG_CLIENT_BLKID_gdc_one_8                       = 0x5b,
5298 	DBG_CLIENT_BLKID_gdc_one_9                       = 0x5c,
5299 	DBG_CLIENT_BLKID_gdc_one_10                      = 0x5d,
5300 	DBG_CLIENT_BLKID_gdc_one_11                      = 0x5e,
5301 	DBG_CLIENT_BLKID_gdc_one_12                      = 0x5f,
5302 	DBG_CLIENT_BLKID_gdc_one_13                      = 0x60,
5303 	DBG_CLIENT_BLKID_gdc_one_14                      = 0x61,
5304 	DBG_CLIENT_BLKID_gdc_one_15                      = 0x62,
5305 	DBG_CLIENT_BLKID_gdc_one_16                      = 0x63,
5306 	DBG_CLIENT_BLKID_gdc_one_17                      = 0x64,
5307 	DBG_CLIENT_BLKID_gdc_one_18                      = 0x65,
5308 	DBG_CLIENT_BLKID_gdc_one_19                      = 0x66,
5309 	DBG_CLIENT_BLKID_gdc_one_20                      = 0x67,
5310 	DBG_CLIENT_BLKID_gdc_one_21                      = 0x68,
5311 	DBG_CLIENT_BLKID_gdc_one_22                      = 0x69,
5312 	DBG_CLIENT_BLKID_gdc_one_23                      = 0x6a,
5313 	DBG_CLIENT_BLKID_gdc_one_24                      = 0x6b,
5314 	DBG_CLIENT_BLKID_gdc_one_25                      = 0x6c,
5315 	DBG_CLIENT_BLKID_gdc_one_26                      = 0x6d,
5316 	DBG_CLIENT_BLKID_gdc_one_27                      = 0x6e,
5317 	DBG_CLIENT_BLKID_gdc_one_28                      = 0x6f,
5318 	DBG_CLIENT_BLKID_gdc_one_29                      = 0x70,
5319 	DBG_CLIENT_BLKID_gdc_one_30                      = 0x71,
5320 	DBG_CLIENT_BLKID_gdc_one_31                      = 0x72,
5321 	DBG_CLIENT_BLKID_gdc_one_32                      = 0x73,
5322 	DBG_CLIENT_BLKID_gdc_one_33                      = 0x74,
5323 	DBG_CLIENT_BLKID_gdc_one_34                      = 0x75,
5324 	DBG_CLIENT_BLKID_gdc_one_35                      = 0x76,
5325 	DBG_CLIENT_BLKID_vceb0_0                         = 0x77,
5326 	DBG_CLIENT_BLKID_vgt3                            = 0x78,
5327 	DBG_CLIENT_BLKID_pc3                             = 0x79,
5328 	DBG_CLIENT_BLKID_mcd3                            = 0x7a,
5329 	DBG_CLIENT_BLKID_uvdu_0                          = 0x7b,
5330 	DBG_CLIENT_BLKID_uvdu_1                          = 0x7c,
5331 	DBG_CLIENT_BLKID_uvdu_2                          = 0x7d,
5332 	DBG_CLIENT_BLKID_uvdu_3                          = 0x7e,
5333 	DBG_CLIENT_BLKID_uvdu_4                          = 0x7f,
5334 	DBG_CLIENT_BLKID_uvdu_5                          = 0x80,
5335 	DBG_CLIENT_BLKID_uvdu_6                          = 0x81,
5336 	DBG_CLIENT_BLKID_cb300                           = 0x82,
5337 	DBG_CLIENT_BLKID_mcd1                            = 0x83,
5338 	DBG_CLIENT_BLKID_sx00                            = 0x84,
5339 	DBG_CLIENT_BLKID_uvdf_0                          = 0x85,
5340 	DBG_CLIENT_BLKID_uvdf_1                          = 0x86,
5341 	DBG_CLIENT_BLKID_mcc3                            = 0x87,
5342 	DBG_CLIENT_BLKID_cpg_0                           = 0x88,
5343 	DBG_CLIENT_BLKID_cpg_1                           = 0x89,
5344 	DBG_CLIENT_BLKID_gck                             = 0x8a,
5345 	DBG_CLIENT_BLKID_mcc1                            = 0x8b,
5346 	DBG_CLIENT_BLKID_cpf_0                           = 0x8c,
5347 	DBG_CLIENT_BLKID_cpf_1                           = 0x8d,
5348 	DBG_CLIENT_BLKID_rlc                             = 0x8e,
5349 	DBG_CLIENT_BLKID_grbm                            = 0x8f,
5350 	DBG_CLIENT_BLKID_sammsp                          = 0x90,
5351 	DBG_CLIENT_BLKID_dci_pg                          = 0x91,
5352 	DBG_CLIENT_BLKID_dci_0                           = 0x92,
5353 	DBG_CLIENT_BLKID_dccg0_0                         = 0x93,
5354 	DBG_CLIENT_BLKID_dccg0_1                         = 0x94,
5355 	DBG_CLIENT_BLKID_dccg0_2                         = 0x95,
5356 	DBG_CLIENT_BLKID_dccg0_3                         = 0x96,
5357 	DBG_CLIENT_BLKID_dccg0_4                         = 0x97,
5358 	DBG_CLIENT_BLKID_dccg0_5                         = 0x98,
5359 	DBG_CLIENT_BLKID_dccg0_6                         = 0x99,
5360 	DBG_CLIENT_BLKID_dccg0_7                         = 0x9a,
5361 	DBG_CLIENT_BLKID_dccg0_8                         = 0x9b,
5362 	DBG_CLIENT_BLKID_dcfe01_0                        = 0x9c,
5363 	DBG_CLIENT_BLKID_dcfe02_0                        = 0x9d,
5364 	DBG_CLIENT_BLKID_dcfe03_0                        = 0x9e,
5365 	DBG_CLIENT_BLKID_dcfe04_0                        = 0x9f,
5366 	DBG_CLIENT_BLKID_dcfe05_0                        = 0xa0,
5367 	DBG_CLIENT_BLKID_dcfe06_0                        = 0xa1,
5368 	DBG_CLIENT_BLKID_uvde_0                          = 0xa2,
5369 	DBG_CLIENT_BLKID_RESERVED_LAST                   = 0xa3,
5370 } DebugBlockId;
5371 typedef enum DebugBlockId_OLD {
5372 	DBG_BLOCK_ID_RESERVED                            = 0x0,
5373 	DBG_BLOCK_ID_DBG                                 = 0x1,
5374 	DBG_BLOCK_ID_VMC                                 = 0x2,
5375 	DBG_BLOCK_ID_PDMA                                = 0x3,
5376 	DBG_BLOCK_ID_CG                                  = 0x4,
5377 	DBG_BLOCK_ID_SRBM                                = 0x5,
5378 	DBG_BLOCK_ID_GRBM                                = 0x6,
5379 	DBG_BLOCK_ID_RLC                                 = 0x7,
5380 	DBG_BLOCK_ID_CSC                                 = 0x8,
5381 	DBG_BLOCK_ID_SEM                                 = 0x9,
5382 	DBG_BLOCK_ID_IH                                  = 0xa,
5383 	DBG_BLOCK_ID_SC                                  = 0xb,
5384 	DBG_BLOCK_ID_SQ                                  = 0xc,
5385 	DBG_BLOCK_ID_AVP                                 = 0xd,
5386 	DBG_BLOCK_ID_GMCON                               = 0xe,
5387 	DBG_BLOCK_ID_SMU                                 = 0xf,
5388 	DBG_BLOCK_ID_DMA0                                = 0x10,
5389 	DBG_BLOCK_ID_DMA1                                = 0x11,
5390 	DBG_BLOCK_ID_SPIM                                = 0x12,
5391 	DBG_BLOCK_ID_GDS                                 = 0x13,
5392 	DBG_BLOCK_ID_SPIS                                = 0x14,
5393 	DBG_BLOCK_ID_UNUSED0                             = 0x15,
5394 	DBG_BLOCK_ID_PA0                                 = 0x16,
5395 	DBG_BLOCK_ID_PA1                                 = 0x17,
5396 	DBG_BLOCK_ID_CP0                                 = 0x18,
5397 	DBG_BLOCK_ID_CP1                                 = 0x19,
5398 	DBG_BLOCK_ID_CP2                                 = 0x1a,
5399 	DBG_BLOCK_ID_UNUSED1                             = 0x1b,
5400 	DBG_BLOCK_ID_UVDU                                = 0x1c,
5401 	DBG_BLOCK_ID_UVDM                                = 0x1d,
5402 	DBG_BLOCK_ID_VCE                                 = 0x1e,
5403 	DBG_BLOCK_ID_UNUSED2                             = 0x1f,
5404 	DBG_BLOCK_ID_VGT0                                = 0x20,
5405 	DBG_BLOCK_ID_VGT1                                = 0x21,
5406 	DBG_BLOCK_ID_IA                                  = 0x22,
5407 	DBG_BLOCK_ID_UNUSED3                             = 0x23,
5408 	DBG_BLOCK_ID_SCT0                                = 0x24,
5409 	DBG_BLOCK_ID_SCT1                                = 0x25,
5410 	DBG_BLOCK_ID_SPM0                                = 0x26,
5411 	DBG_BLOCK_ID_SPM1                                = 0x27,
5412 	DBG_BLOCK_ID_TCAA                                = 0x28,
5413 	DBG_BLOCK_ID_TCAB                                = 0x29,
5414 	DBG_BLOCK_ID_TCCA                                = 0x2a,
5415 	DBG_BLOCK_ID_TCCB                                = 0x2b,
5416 	DBG_BLOCK_ID_MCC0                                = 0x2c,
5417 	DBG_BLOCK_ID_MCC1                                = 0x2d,
5418 	DBG_BLOCK_ID_MCC2                                = 0x2e,
5419 	DBG_BLOCK_ID_MCC3                                = 0x2f,
5420 	DBG_BLOCK_ID_SX0                                 = 0x30,
5421 	DBG_BLOCK_ID_SX1                                 = 0x31,
5422 	DBG_BLOCK_ID_SX2                                 = 0x32,
5423 	DBG_BLOCK_ID_SX3                                 = 0x33,
5424 	DBG_BLOCK_ID_UNUSED4                             = 0x34,
5425 	DBG_BLOCK_ID_UNUSED5                             = 0x35,
5426 	DBG_BLOCK_ID_UNUSED6                             = 0x36,
5427 	DBG_BLOCK_ID_UNUSED7                             = 0x37,
5428 	DBG_BLOCK_ID_PC0                                 = 0x38,
5429 	DBG_BLOCK_ID_PC1                                 = 0x39,
5430 	DBG_BLOCK_ID_UNUSED8                             = 0x3a,
5431 	DBG_BLOCK_ID_UNUSED9                             = 0x3b,
5432 	DBG_BLOCK_ID_UNUSED10                            = 0x3c,
5433 	DBG_BLOCK_ID_UNUSED11                            = 0x3d,
5434 	DBG_BLOCK_ID_MCB                                 = 0x3e,
5435 	DBG_BLOCK_ID_UNUSED12                            = 0x3f,
5436 	DBG_BLOCK_ID_SCB0                                = 0x40,
5437 	DBG_BLOCK_ID_SCB1                                = 0x41,
5438 	DBG_BLOCK_ID_UNUSED13                            = 0x42,
5439 	DBG_BLOCK_ID_UNUSED14                            = 0x43,
5440 	DBG_BLOCK_ID_SCF0                                = 0x44,
5441 	DBG_BLOCK_ID_SCF1                                = 0x45,
5442 	DBG_BLOCK_ID_UNUSED15                            = 0x46,
5443 	DBG_BLOCK_ID_UNUSED16                            = 0x47,
5444 	DBG_BLOCK_ID_BCI0                                = 0x48,
5445 	DBG_BLOCK_ID_BCI1                                = 0x49,
5446 	DBG_BLOCK_ID_BCI2                                = 0x4a,
5447 	DBG_BLOCK_ID_BCI3                                = 0x4b,
5448 	DBG_BLOCK_ID_UNUSED17                            = 0x4c,
5449 	DBG_BLOCK_ID_UNUSED18                            = 0x4d,
5450 	DBG_BLOCK_ID_UNUSED19                            = 0x4e,
5451 	DBG_BLOCK_ID_UNUSED20                            = 0x4f,
5452 	DBG_BLOCK_ID_CB00                                = 0x50,
5453 	DBG_BLOCK_ID_CB01                                = 0x51,
5454 	DBG_BLOCK_ID_CB02                                = 0x52,
5455 	DBG_BLOCK_ID_CB03                                = 0x53,
5456 	DBG_BLOCK_ID_CB04                                = 0x54,
5457 	DBG_BLOCK_ID_UNUSED21                            = 0x55,
5458 	DBG_BLOCK_ID_UNUSED22                            = 0x56,
5459 	DBG_BLOCK_ID_UNUSED23                            = 0x57,
5460 	DBG_BLOCK_ID_CB10                                = 0x58,
5461 	DBG_BLOCK_ID_CB11                                = 0x59,
5462 	DBG_BLOCK_ID_CB12                                = 0x5a,
5463 	DBG_BLOCK_ID_CB13                                = 0x5b,
5464 	DBG_BLOCK_ID_CB14                                = 0x5c,
5465 	DBG_BLOCK_ID_UNUSED24                            = 0x5d,
5466 	DBG_BLOCK_ID_UNUSED25                            = 0x5e,
5467 	DBG_BLOCK_ID_UNUSED26                            = 0x5f,
5468 	DBG_BLOCK_ID_TCP0                                = 0x60,
5469 	DBG_BLOCK_ID_TCP1                                = 0x61,
5470 	DBG_BLOCK_ID_TCP2                                = 0x62,
5471 	DBG_BLOCK_ID_TCP3                                = 0x63,
5472 	DBG_BLOCK_ID_TCP4                                = 0x64,
5473 	DBG_BLOCK_ID_TCP5                                = 0x65,
5474 	DBG_BLOCK_ID_TCP6                                = 0x66,
5475 	DBG_BLOCK_ID_TCP7                                = 0x67,
5476 	DBG_BLOCK_ID_TCP8                                = 0x68,
5477 	DBG_BLOCK_ID_TCP9                                = 0x69,
5478 	DBG_BLOCK_ID_TCP10                               = 0x6a,
5479 	DBG_BLOCK_ID_TCP11                               = 0x6b,
5480 	DBG_BLOCK_ID_TCP12                               = 0x6c,
5481 	DBG_BLOCK_ID_TCP13                               = 0x6d,
5482 	DBG_BLOCK_ID_TCP14                               = 0x6e,
5483 	DBG_BLOCK_ID_TCP15                               = 0x6f,
5484 	DBG_BLOCK_ID_TCP16                               = 0x70,
5485 	DBG_BLOCK_ID_TCP17                               = 0x71,
5486 	DBG_BLOCK_ID_TCP18                               = 0x72,
5487 	DBG_BLOCK_ID_TCP19                               = 0x73,
5488 	DBG_BLOCK_ID_TCP20                               = 0x74,
5489 	DBG_BLOCK_ID_TCP21                               = 0x75,
5490 	DBG_BLOCK_ID_TCP22                               = 0x76,
5491 	DBG_BLOCK_ID_TCP23                               = 0x77,
5492 	DBG_BLOCK_ID_TCP_RESERVED0                       = 0x78,
5493 	DBG_BLOCK_ID_TCP_RESERVED1                       = 0x79,
5494 	DBG_BLOCK_ID_TCP_RESERVED2                       = 0x7a,
5495 	DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7b,
5496 	DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7c,
5497 	DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7d,
5498 	DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7e,
5499 	DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7f,
5500 	DBG_BLOCK_ID_DB00                                = 0x80,
5501 	DBG_BLOCK_ID_DB01                                = 0x81,
5502 	DBG_BLOCK_ID_DB02                                = 0x82,
5503 	DBG_BLOCK_ID_DB03                                = 0x83,
5504 	DBG_BLOCK_ID_DB04                                = 0x84,
5505 	DBG_BLOCK_ID_UNUSED27                            = 0x85,
5506 	DBG_BLOCK_ID_UNUSED28                            = 0x86,
5507 	DBG_BLOCK_ID_UNUSED29                            = 0x87,
5508 	DBG_BLOCK_ID_DB10                                = 0x88,
5509 	DBG_BLOCK_ID_DB11                                = 0x89,
5510 	DBG_BLOCK_ID_DB12                                = 0x8a,
5511 	DBG_BLOCK_ID_DB13                                = 0x8b,
5512 	DBG_BLOCK_ID_DB14                                = 0x8c,
5513 	DBG_BLOCK_ID_UNUSED30                            = 0x8d,
5514 	DBG_BLOCK_ID_UNUSED31                            = 0x8e,
5515 	DBG_BLOCK_ID_UNUSED32                            = 0x8f,
5516 	DBG_BLOCK_ID_TCC0                                = 0x90,
5517 	DBG_BLOCK_ID_TCC1                                = 0x91,
5518 	DBG_BLOCK_ID_TCC2                                = 0x92,
5519 	DBG_BLOCK_ID_TCC3                                = 0x93,
5520 	DBG_BLOCK_ID_TCC4                                = 0x94,
5521 	DBG_BLOCK_ID_TCC5                                = 0x95,
5522 	DBG_BLOCK_ID_TCC6                                = 0x96,
5523 	DBG_BLOCK_ID_TCC7                                = 0x97,
5524 	DBG_BLOCK_ID_SPS00                               = 0x98,
5525 	DBG_BLOCK_ID_SPS01                               = 0x99,
5526 	DBG_BLOCK_ID_SPS02                               = 0x9a,
5527 	DBG_BLOCK_ID_SPS10                               = 0x9b,
5528 	DBG_BLOCK_ID_SPS11                               = 0x9c,
5529 	DBG_BLOCK_ID_SPS12                               = 0x9d,
5530 	DBG_BLOCK_ID_UNUSED33                            = 0x9e,
5531 	DBG_BLOCK_ID_UNUSED34                            = 0x9f,
5532 	DBG_BLOCK_ID_TA00                                = 0xa0,
5533 	DBG_BLOCK_ID_TA01                                = 0xa1,
5534 	DBG_BLOCK_ID_TA02                                = 0xa2,
5535 	DBG_BLOCK_ID_TA03                                = 0xa3,
5536 	DBG_BLOCK_ID_TA04                                = 0xa4,
5537 	DBG_BLOCK_ID_TA05                                = 0xa5,
5538 	DBG_BLOCK_ID_TA06                                = 0xa6,
5539 	DBG_BLOCK_ID_TA07                                = 0xa7,
5540 	DBG_BLOCK_ID_TA08                                = 0xa8,
5541 	DBG_BLOCK_ID_TA09                                = 0xa9,
5542 	DBG_BLOCK_ID_TA0A                                = 0xaa,
5543 	DBG_BLOCK_ID_TA0B                                = 0xab,
5544 	DBG_BLOCK_ID_UNUSED35                            = 0xac,
5545 	DBG_BLOCK_ID_UNUSED36                            = 0xad,
5546 	DBG_BLOCK_ID_UNUSED37                            = 0xae,
5547 	DBG_BLOCK_ID_UNUSED38                            = 0xaf,
5548 	DBG_BLOCK_ID_TA10                                = 0xb0,
5549 	DBG_BLOCK_ID_TA11                                = 0xb1,
5550 	DBG_BLOCK_ID_TA12                                = 0xb2,
5551 	DBG_BLOCK_ID_TA13                                = 0xb3,
5552 	DBG_BLOCK_ID_TA14                                = 0xb4,
5553 	DBG_BLOCK_ID_TA15                                = 0xb5,
5554 	DBG_BLOCK_ID_TA16                                = 0xb6,
5555 	DBG_BLOCK_ID_TA17                                = 0xb7,
5556 	DBG_BLOCK_ID_TA18                                = 0xb8,
5557 	DBG_BLOCK_ID_TA19                                = 0xb9,
5558 	DBG_BLOCK_ID_TA1A                                = 0xba,
5559 	DBG_BLOCK_ID_TA1B                                = 0xbb,
5560 	DBG_BLOCK_ID_UNUSED39                            = 0xbc,
5561 	DBG_BLOCK_ID_UNUSED40                            = 0xbd,
5562 	DBG_BLOCK_ID_UNUSED41                            = 0xbe,
5563 	DBG_BLOCK_ID_UNUSED42                            = 0xbf,
5564 	DBG_BLOCK_ID_TD00                                = 0xc0,
5565 	DBG_BLOCK_ID_TD01                                = 0xc1,
5566 	DBG_BLOCK_ID_TD02                                = 0xc2,
5567 	DBG_BLOCK_ID_TD03                                = 0xc3,
5568 	DBG_BLOCK_ID_TD04                                = 0xc4,
5569 	DBG_BLOCK_ID_TD05                                = 0xc5,
5570 	DBG_BLOCK_ID_TD06                                = 0xc6,
5571 	DBG_BLOCK_ID_TD07                                = 0xc7,
5572 	DBG_BLOCK_ID_TD08                                = 0xc8,
5573 	DBG_BLOCK_ID_TD09                                = 0xc9,
5574 	DBG_BLOCK_ID_TD0A                                = 0xca,
5575 	DBG_BLOCK_ID_TD0B                                = 0xcb,
5576 	DBG_BLOCK_ID_UNUSED43                            = 0xcc,
5577 	DBG_BLOCK_ID_UNUSED44                            = 0xcd,
5578 	DBG_BLOCK_ID_UNUSED45                            = 0xce,
5579 	DBG_BLOCK_ID_UNUSED46                            = 0xcf,
5580 	DBG_BLOCK_ID_TD10                                = 0xd0,
5581 	DBG_BLOCK_ID_TD11                                = 0xd1,
5582 	DBG_BLOCK_ID_TD12                                = 0xd2,
5583 	DBG_BLOCK_ID_TD13                                = 0xd3,
5584 	DBG_BLOCK_ID_TD14                                = 0xd4,
5585 	DBG_BLOCK_ID_TD15                                = 0xd5,
5586 	DBG_BLOCK_ID_TD16                                = 0xd6,
5587 	DBG_BLOCK_ID_TD17                                = 0xd7,
5588 	DBG_BLOCK_ID_TD18                                = 0xd8,
5589 	DBG_BLOCK_ID_TD19                                = 0xd9,
5590 	DBG_BLOCK_ID_TD1A                                = 0xda,
5591 	DBG_BLOCK_ID_TD1B                                = 0xdb,
5592 	DBG_BLOCK_ID_UNUSED47                            = 0xdc,
5593 	DBG_BLOCK_ID_UNUSED48                            = 0xdd,
5594 	DBG_BLOCK_ID_UNUSED49                            = 0xde,
5595 	DBG_BLOCK_ID_UNUSED50                            = 0xdf,
5596 	DBG_BLOCK_ID_MCD0                                = 0xe0,
5597 	DBG_BLOCK_ID_MCD1                                = 0xe1,
5598 	DBG_BLOCK_ID_MCD2                                = 0xe2,
5599 	DBG_BLOCK_ID_MCD3                                = 0xe3,
5600 	DBG_BLOCK_ID_MCD4                                = 0xe4,
5601 	DBG_BLOCK_ID_MCD5                                = 0xe5,
5602 	DBG_BLOCK_ID_UNUSED51                            = 0xe6,
5603 	DBG_BLOCK_ID_UNUSED52                            = 0xe7,
5604 } DebugBlockId_OLD;
5605 typedef enum DebugBlockId_BY2 {
5606 	DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
5607 	DBG_BLOCK_ID_VMC_BY2                             = 0x1,
5608 	DBG_BLOCK_ID_CG_BY2                              = 0x2,
5609 	DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
5610 	DBG_BLOCK_ID_CSC_BY2                             = 0x4,
5611 	DBG_BLOCK_ID_IH_BY2                              = 0x5,
5612 	DBG_BLOCK_ID_SQ_BY2                              = 0x6,
5613 	DBG_BLOCK_ID_GMCON_BY2                           = 0x7,
5614 	DBG_BLOCK_ID_DMA0_BY2                            = 0x8,
5615 	DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
5616 	DBG_BLOCK_ID_SPIS_BY2                            = 0xa,
5617 	DBG_BLOCK_ID_PA0_BY2                             = 0xb,
5618 	DBG_BLOCK_ID_CP0_BY2                             = 0xc,
5619 	DBG_BLOCK_ID_CP2_BY2                             = 0xd,
5620 	DBG_BLOCK_ID_UVDU_BY2                            = 0xe,
5621 	DBG_BLOCK_ID_VCE_BY2                             = 0xf,
5622 	DBG_BLOCK_ID_VGT0_BY2                            = 0x10,
5623 	DBG_BLOCK_ID_IA_BY2                              = 0x11,
5624 	DBG_BLOCK_ID_SCT0_BY2                            = 0x12,
5625 	DBG_BLOCK_ID_SPM0_BY2                            = 0x13,
5626 	DBG_BLOCK_ID_TCAA_BY2                            = 0x14,
5627 	DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
5628 	DBG_BLOCK_ID_MCC0_BY2                            = 0x16,
5629 	DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
5630 	DBG_BLOCK_ID_SX0_BY2                             = 0x18,
5631 	DBG_BLOCK_ID_SX2_BY2                             = 0x19,
5632 	DBG_BLOCK_ID_UNUSED4_BY2                         = 0x1a,
5633 	DBG_BLOCK_ID_UNUSED6_BY2                         = 0x1b,
5634 	DBG_BLOCK_ID_PC0_BY2                             = 0x1c,
5635 	DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1d,
5636 	DBG_BLOCK_ID_UNUSED10_BY2                        = 0x1e,
5637 	DBG_BLOCK_ID_MCB_BY2                             = 0x1f,
5638 	DBG_BLOCK_ID_SCB0_BY2                            = 0x20,
5639 	DBG_BLOCK_ID_UNUSED13_BY2                        = 0x21,
5640 	DBG_BLOCK_ID_SCF0_BY2                            = 0x22,
5641 	DBG_BLOCK_ID_UNUSED15_BY2                        = 0x23,
5642 	DBG_BLOCK_ID_BCI0_BY2                            = 0x24,
5643 	DBG_BLOCK_ID_BCI2_BY2                            = 0x25,
5644 	DBG_BLOCK_ID_UNUSED17_BY2                        = 0x26,
5645 	DBG_BLOCK_ID_UNUSED19_BY2                        = 0x27,
5646 	DBG_BLOCK_ID_CB00_BY2                            = 0x28,
5647 	DBG_BLOCK_ID_CB02_BY2                            = 0x29,
5648 	DBG_BLOCK_ID_CB04_BY2                            = 0x2a,
5649 	DBG_BLOCK_ID_UNUSED22_BY2                        = 0x2b,
5650 	DBG_BLOCK_ID_CB10_BY2                            = 0x2c,
5651 	DBG_BLOCK_ID_CB12_BY2                            = 0x2d,
5652 	DBG_BLOCK_ID_CB14_BY2                            = 0x2e,
5653 	DBG_BLOCK_ID_UNUSED25_BY2                        = 0x2f,
5654 	DBG_BLOCK_ID_TCP0_BY2                            = 0x30,
5655 	DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
5656 	DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
5657 	DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
5658 	DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
5659 	DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
5660 	DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
5661 	DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
5662 	DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
5663 	DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
5664 	DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
5665 	DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
5666 	DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
5667 	DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
5668 	DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
5669 	DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
5670 	DBG_BLOCK_ID_DB00_BY2                            = 0x40,
5671 	DBG_BLOCK_ID_DB02_BY2                            = 0x41,
5672 	DBG_BLOCK_ID_DB04_BY2                            = 0x42,
5673 	DBG_BLOCK_ID_UNUSED28_BY2                        = 0x43,
5674 	DBG_BLOCK_ID_DB10_BY2                            = 0x44,
5675 	DBG_BLOCK_ID_DB12_BY2                            = 0x45,
5676 	DBG_BLOCK_ID_DB14_BY2                            = 0x46,
5677 	DBG_BLOCK_ID_UNUSED31_BY2                        = 0x47,
5678 	DBG_BLOCK_ID_TCC0_BY2                            = 0x48,
5679 	DBG_BLOCK_ID_TCC2_BY2                            = 0x49,
5680 	DBG_BLOCK_ID_TCC4_BY2                            = 0x4a,
5681 	DBG_BLOCK_ID_TCC6_BY2                            = 0x4b,
5682 	DBG_BLOCK_ID_SPS00_BY2                           = 0x4c,
5683 	DBG_BLOCK_ID_SPS02_BY2                           = 0x4d,
5684 	DBG_BLOCK_ID_SPS11_BY2                           = 0x4e,
5685 	DBG_BLOCK_ID_UNUSED33_BY2                        = 0x4f,
5686 	DBG_BLOCK_ID_TA00_BY2                            = 0x50,
5687 	DBG_BLOCK_ID_TA02_BY2                            = 0x51,
5688 	DBG_BLOCK_ID_TA04_BY2                            = 0x52,
5689 	DBG_BLOCK_ID_TA06_BY2                            = 0x53,
5690 	DBG_BLOCK_ID_TA08_BY2                            = 0x54,
5691 	DBG_BLOCK_ID_TA0A_BY2                            = 0x55,
5692 	DBG_BLOCK_ID_UNUSED35_BY2                        = 0x56,
5693 	DBG_BLOCK_ID_UNUSED37_BY2                        = 0x57,
5694 	DBG_BLOCK_ID_TA10_BY2                            = 0x58,
5695 	DBG_BLOCK_ID_TA12_BY2                            = 0x59,
5696 	DBG_BLOCK_ID_TA14_BY2                            = 0x5a,
5697 	DBG_BLOCK_ID_TA16_BY2                            = 0x5b,
5698 	DBG_BLOCK_ID_TA18_BY2                            = 0x5c,
5699 	DBG_BLOCK_ID_TA1A_BY2                            = 0x5d,
5700 	DBG_BLOCK_ID_UNUSED39_BY2                        = 0x5e,
5701 	DBG_BLOCK_ID_UNUSED41_BY2                        = 0x5f,
5702 	DBG_BLOCK_ID_TD00_BY2                            = 0x60,
5703 	DBG_BLOCK_ID_TD02_BY2                            = 0x61,
5704 	DBG_BLOCK_ID_TD04_BY2                            = 0x62,
5705 	DBG_BLOCK_ID_TD06_BY2                            = 0x63,
5706 	DBG_BLOCK_ID_TD08_BY2                            = 0x64,
5707 	DBG_BLOCK_ID_TD0A_BY2                            = 0x65,
5708 	DBG_BLOCK_ID_UNUSED43_BY2                        = 0x66,
5709 	DBG_BLOCK_ID_UNUSED45_BY2                        = 0x67,
5710 	DBG_BLOCK_ID_TD10_BY2                            = 0x68,
5711 	DBG_BLOCK_ID_TD12_BY2                            = 0x69,
5712 	DBG_BLOCK_ID_TD14_BY2                            = 0x6a,
5713 	DBG_BLOCK_ID_TD16_BY2                            = 0x6b,
5714 	DBG_BLOCK_ID_TD18_BY2                            = 0x6c,
5715 	DBG_BLOCK_ID_TD1A_BY2                            = 0x6d,
5716 	DBG_BLOCK_ID_UNUSED47_BY2                        = 0x6e,
5717 	DBG_BLOCK_ID_UNUSED49_BY2                        = 0x6f,
5718 	DBG_BLOCK_ID_MCD0_BY2                            = 0x70,
5719 	DBG_BLOCK_ID_MCD2_BY2                            = 0x71,
5720 	DBG_BLOCK_ID_MCD4_BY2                            = 0x72,
5721 	DBG_BLOCK_ID_UNUSED51_BY2                        = 0x73,
5722 } DebugBlockId_BY2;
5723 typedef enum DebugBlockId_BY4 {
5724 	DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
5725 	DBG_BLOCK_ID_CG_BY4                              = 0x1,
5726 	DBG_BLOCK_ID_CSC_BY4                             = 0x2,
5727 	DBG_BLOCK_ID_SQ_BY4                              = 0x3,
5728 	DBG_BLOCK_ID_DMA0_BY4                            = 0x4,
5729 	DBG_BLOCK_ID_SPIS_BY4                            = 0x5,
5730 	DBG_BLOCK_ID_CP0_BY4                             = 0x6,
5731 	DBG_BLOCK_ID_UVDU_BY4                            = 0x7,
5732 	DBG_BLOCK_ID_VGT0_BY4                            = 0x8,
5733 	DBG_BLOCK_ID_SCT0_BY4                            = 0x9,
5734 	DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
5735 	DBG_BLOCK_ID_MCC0_BY4                            = 0xb,
5736 	DBG_BLOCK_ID_SX0_BY4                             = 0xc,
5737 	DBG_BLOCK_ID_UNUSED4_BY4                         = 0xd,
5738 	DBG_BLOCK_ID_PC0_BY4                             = 0xe,
5739 	DBG_BLOCK_ID_UNUSED10_BY4                        = 0xf,
5740 	DBG_BLOCK_ID_SCB0_BY4                            = 0x10,
5741 	DBG_BLOCK_ID_SCF0_BY4                            = 0x11,
5742 	DBG_BLOCK_ID_BCI0_BY4                            = 0x12,
5743 	DBG_BLOCK_ID_UNUSED17_BY4                        = 0x13,
5744 	DBG_BLOCK_ID_CB00_BY4                            = 0x14,
5745 	DBG_BLOCK_ID_CB04_BY4                            = 0x15,
5746 	DBG_BLOCK_ID_CB10_BY4                            = 0x16,
5747 	DBG_BLOCK_ID_CB14_BY4                            = 0x17,
5748 	DBG_BLOCK_ID_TCP0_BY4                            = 0x18,
5749 	DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
5750 	DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
5751 	DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
5752 	DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
5753 	DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
5754 	DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
5755 	DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
5756 	DBG_BLOCK_ID_DB_BY4                              = 0x20,
5757 	DBG_BLOCK_ID_DB04_BY4                            = 0x21,
5758 	DBG_BLOCK_ID_DB10_BY4                            = 0x22,
5759 	DBG_BLOCK_ID_DB14_BY4                            = 0x23,
5760 	DBG_BLOCK_ID_TCC0_BY4                            = 0x24,
5761 	DBG_BLOCK_ID_TCC4_BY4                            = 0x25,
5762 	DBG_BLOCK_ID_SPS00_BY4                           = 0x26,
5763 	DBG_BLOCK_ID_SPS11_BY4                           = 0x27,
5764 	DBG_BLOCK_ID_TA00_BY4                            = 0x28,
5765 	DBG_BLOCK_ID_TA04_BY4                            = 0x29,
5766 	DBG_BLOCK_ID_TA08_BY4                            = 0x2a,
5767 	DBG_BLOCK_ID_UNUSED35_BY4                        = 0x2b,
5768 	DBG_BLOCK_ID_TA10_BY4                            = 0x2c,
5769 	DBG_BLOCK_ID_TA14_BY4                            = 0x2d,
5770 	DBG_BLOCK_ID_TA18_BY4                            = 0x2e,
5771 	DBG_BLOCK_ID_UNUSED39_BY4                        = 0x2f,
5772 	DBG_BLOCK_ID_TD00_BY4                            = 0x30,
5773 	DBG_BLOCK_ID_TD04_BY4                            = 0x31,
5774 	DBG_BLOCK_ID_TD08_BY4                            = 0x32,
5775 	DBG_BLOCK_ID_UNUSED43_BY4                        = 0x33,
5776 	DBG_BLOCK_ID_TD10_BY4                            = 0x34,
5777 	DBG_BLOCK_ID_TD14_BY4                            = 0x35,
5778 	DBG_BLOCK_ID_TD18_BY4                            = 0x36,
5779 	DBG_BLOCK_ID_UNUSED47_BY4                        = 0x37,
5780 	DBG_BLOCK_ID_MCD0_BY4                            = 0x38,
5781 	DBG_BLOCK_ID_MCD4_BY4                            = 0x39,
5782 } DebugBlockId_BY4;
5783 typedef enum DebugBlockId_BY8 {
5784 	DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
5785 	DBG_BLOCK_ID_CSC_BY8                             = 0x1,
5786 	DBG_BLOCK_ID_DMA0_BY8                            = 0x2,
5787 	DBG_BLOCK_ID_CP0_BY8                             = 0x3,
5788 	DBG_BLOCK_ID_VGT0_BY8                            = 0x4,
5789 	DBG_BLOCK_ID_TCAA_BY8                            = 0x5,
5790 	DBG_BLOCK_ID_SX0_BY8                             = 0x6,
5791 	DBG_BLOCK_ID_PC0_BY8                             = 0x7,
5792 	DBG_BLOCK_ID_SCB0_BY8                            = 0x8,
5793 	DBG_BLOCK_ID_BCI0_BY8                            = 0x9,
5794 	DBG_BLOCK_ID_CB00_BY8                            = 0xa,
5795 	DBG_BLOCK_ID_CB10_BY8                            = 0xb,
5796 	DBG_BLOCK_ID_TCP0_BY8                            = 0xc,
5797 	DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
5798 	DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
5799 	DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
5800 	DBG_BLOCK_ID_DB00_BY8                            = 0x10,
5801 	DBG_BLOCK_ID_DB10_BY8                            = 0x11,
5802 	DBG_BLOCK_ID_TCC0_BY8                            = 0x12,
5803 	DBG_BLOCK_ID_SPS00_BY8                           = 0x13,
5804 	DBG_BLOCK_ID_TA00_BY8                            = 0x14,
5805 	DBG_BLOCK_ID_TA08_BY8                            = 0x15,
5806 	DBG_BLOCK_ID_TA10_BY8                            = 0x16,
5807 	DBG_BLOCK_ID_TA18_BY8                            = 0x17,
5808 	DBG_BLOCK_ID_TD00_BY8                            = 0x18,
5809 	DBG_BLOCK_ID_TD08_BY8                            = 0x19,
5810 	DBG_BLOCK_ID_TD10_BY8                            = 0x1a,
5811 	DBG_BLOCK_ID_TD18_BY8                            = 0x1b,
5812 	DBG_BLOCK_ID_MCD0_BY8                            = 0x1c,
5813 } DebugBlockId_BY8;
5814 typedef enum DebugBlockId_BY16 {
5815 	DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
5816 	DBG_BLOCK_ID_DMA0_BY16                           = 0x1,
5817 	DBG_BLOCK_ID_VGT0_BY16                           = 0x2,
5818 	DBG_BLOCK_ID_SX0_BY16                            = 0x3,
5819 	DBG_BLOCK_ID_SCB0_BY16                           = 0x4,
5820 	DBG_BLOCK_ID_CB00_BY16                           = 0x5,
5821 	DBG_BLOCK_ID_TCP0_BY16                           = 0x6,
5822 	DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
5823 	DBG_BLOCK_ID_DB00_BY16                           = 0x8,
5824 	DBG_BLOCK_ID_TCC0_BY16                           = 0x9,
5825 	DBG_BLOCK_ID_TA00_BY16                           = 0xa,
5826 	DBG_BLOCK_ID_TA10_BY16                           = 0xb,
5827 	DBG_BLOCK_ID_TD00_BY16                           = 0xc,
5828 	DBG_BLOCK_ID_TD10_BY16                           = 0xd,
5829 	DBG_BLOCK_ID_MCD0_BY16                           = 0xe,
5830 } DebugBlockId_BY16;
5831 typedef enum ColorTransform {
5832 	DCC_CT_AUTO                                      = 0x0,
5833 	DCC_CT_NONE                                      = 0x1,
5834 	ABGR_TO_A_BG_G_RB                                = 0x2,
5835 	BGRA_TO_BG_G_RB_A                                = 0x3,
5836 } ColorTransform;
5837 typedef enum CompareRef {
5838 	REF_NEVER                                        = 0x0,
5839 	REF_LESS                                         = 0x1,
5840 	REF_EQUAL                                        = 0x2,
5841 	REF_LEQUAL                                       = 0x3,
5842 	REF_GREATER                                      = 0x4,
5843 	REF_NOTEQUAL                                     = 0x5,
5844 	REF_GEQUAL                                       = 0x6,
5845 	REF_ALWAYS                                       = 0x7,
5846 } CompareRef;
5847 typedef enum ReadSize {
5848 	READ_256_BITS                                    = 0x0,
5849 	READ_512_BITS                                    = 0x1,
5850 } ReadSize;
5851 typedef enum DepthFormat {
5852 	DEPTH_INVALID                                    = 0x0,
5853 	DEPTH_16                                         = 0x1,
5854 	DEPTH_X8_24                                      = 0x2,
5855 	DEPTH_8_24                                       = 0x3,
5856 	DEPTH_X8_24_FLOAT                                = 0x4,
5857 	DEPTH_8_24_FLOAT                                 = 0x5,
5858 	DEPTH_32_FLOAT                                   = 0x6,
5859 	DEPTH_X24_8_32_FLOAT                             = 0x7,
5860 } DepthFormat;
5861 typedef enum ZFormat {
5862 	Z_INVALID                                        = 0x0,
5863 	Z_16                                             = 0x1,
5864 	Z_24                                             = 0x2,
5865 	Z_32_FLOAT                                       = 0x3,
5866 } ZFormat;
5867 typedef enum StencilFormat {
5868 	STENCIL_INVALID                                  = 0x0,
5869 	STENCIL_8                                        = 0x1,
5870 } StencilFormat;
5871 typedef enum CmaskMode {
5872 	CMASK_CLEAR_NONE                                 = 0x0,
5873 	CMASK_CLEAR_ONE                                  = 0x1,
5874 	CMASK_CLEAR_ALL                                  = 0x2,
5875 	CMASK_ANY_EXPANDED                               = 0x3,
5876 	CMASK_ALPHA0_FRAG1                               = 0x4,
5877 	CMASK_ALPHA0_FRAG2                               = 0x5,
5878 	CMASK_ALPHA0_FRAG4                               = 0x6,
5879 	CMASK_ALPHA0_FRAGS                               = 0x7,
5880 	CMASK_ALPHA1_FRAG1                               = 0x8,
5881 	CMASK_ALPHA1_FRAG2                               = 0x9,
5882 	CMASK_ALPHA1_FRAG4                               = 0xa,
5883 	CMASK_ALPHA1_FRAGS                               = 0xb,
5884 	CMASK_ALPHAX_FRAG1                               = 0xc,
5885 	CMASK_ALPHAX_FRAG2                               = 0xd,
5886 	CMASK_ALPHAX_FRAG4                               = 0xe,
5887 	CMASK_ALPHAX_FRAGS                               = 0xf,
5888 } CmaskMode;
5889 typedef enum QuadExportFormat {
5890 	EXPORT_UNUSED                                    = 0x0,
5891 	EXPORT_32_R                                      = 0x1,
5892 	EXPORT_32_GR                                     = 0x2,
5893 	EXPORT_32_AR                                     = 0x3,
5894 	EXPORT_FP16_ABGR                                 = 0x4,
5895 	EXPORT_UNSIGNED16_ABGR                           = 0x5,
5896 	EXPORT_SIGNED16_ABGR                             = 0x6,
5897 	EXPORT_32_ABGR                                   = 0x7,
5898 } QuadExportFormat;
5899 typedef enum QuadExportFormatOld {
5900 	EXPORT_4P_32BPC_ABGR                             = 0x0,
5901 	EXPORT_4P_16BPC_ABGR                             = 0x1,
5902 	EXPORT_4P_32BPC_GR                               = 0x2,
5903 	EXPORT_4P_32BPC_AR                               = 0x3,
5904 	EXPORT_2P_32BPC_ABGR                             = 0x4,
5905 	EXPORT_8P_32BPC_R                                = 0x5,
5906 } QuadExportFormatOld;
5907 typedef enum ColorFormat {
5908 	COLOR_INVALID                                    = 0x0,
5909 	COLOR_8                                          = 0x1,
5910 	COLOR_16                                         = 0x2,
5911 	COLOR_8_8                                        = 0x3,
5912 	COLOR_32                                         = 0x4,
5913 	COLOR_16_16                                      = 0x5,
5914 	COLOR_10_11_11                                   = 0x6,
5915 	COLOR_11_11_10                                   = 0x7,
5916 	COLOR_10_10_10_2                                 = 0x8,
5917 	COLOR_2_10_10_10                                 = 0x9,
5918 	COLOR_8_8_8_8                                    = 0xa,
5919 	COLOR_32_32                                      = 0xb,
5920 	COLOR_16_16_16_16                                = 0xc,
5921 	COLOR_RESERVED_13                                = 0xd,
5922 	COLOR_32_32_32_32                                = 0xe,
5923 	COLOR_RESERVED_15                                = 0xf,
5924 	COLOR_5_6_5                                      = 0x10,
5925 	COLOR_1_5_5_5                                    = 0x11,
5926 	COLOR_5_5_5_1                                    = 0x12,
5927 	COLOR_4_4_4_4                                    = 0x13,
5928 	COLOR_8_24                                       = 0x14,
5929 	COLOR_24_8                                       = 0x15,
5930 	COLOR_X24_8_32_FLOAT                             = 0x16,
5931 	COLOR_RESERVED_23                                = 0x17,
5932 } ColorFormat;
5933 typedef enum SurfaceFormat {
5934 	FMT_INVALID                                      = 0x0,
5935 	FMT_8                                            = 0x1,
5936 	FMT_16                                           = 0x2,
5937 	FMT_8_8                                          = 0x3,
5938 	FMT_32                                           = 0x4,
5939 	FMT_16_16                                        = 0x5,
5940 	FMT_10_11_11                                     = 0x6,
5941 	FMT_11_11_10                                     = 0x7,
5942 	FMT_10_10_10_2                                   = 0x8,
5943 	FMT_2_10_10_10                                   = 0x9,
5944 	FMT_8_8_8_8                                      = 0xa,
5945 	FMT_32_32                                        = 0xb,
5946 	FMT_16_16_16_16                                  = 0xc,
5947 	FMT_32_32_32                                     = 0xd,
5948 	FMT_32_32_32_32                                  = 0xe,
5949 	FMT_RESERVED_4                                   = 0xf,
5950 	FMT_5_6_5                                        = 0x10,
5951 	FMT_1_5_5_5                                      = 0x11,
5952 	FMT_5_5_5_1                                      = 0x12,
5953 	FMT_4_4_4_4                                      = 0x13,
5954 	FMT_8_24                                         = 0x14,
5955 	FMT_24_8                                         = 0x15,
5956 	FMT_X24_8_32_FLOAT                               = 0x16,
5957 	FMT_RESERVED_33                                  = 0x17,
5958 	FMT_11_11_10_FLOAT                               = 0x18,
5959 	FMT_16_FLOAT                                     = 0x19,
5960 	FMT_32_FLOAT                                     = 0x1a,
5961 	FMT_16_16_FLOAT                                  = 0x1b,
5962 	FMT_8_24_FLOAT                                   = 0x1c,
5963 	FMT_24_8_FLOAT                                   = 0x1d,
5964 	FMT_32_32_FLOAT                                  = 0x1e,
5965 	FMT_10_11_11_FLOAT                               = 0x1f,
5966 	FMT_16_16_16_16_FLOAT                            = 0x20,
5967 	FMT_3_3_2                                        = 0x21,
5968 	FMT_6_5_5                                        = 0x22,
5969 	FMT_32_32_32_32_FLOAT                            = 0x23,
5970 	FMT_RESERVED_36                                  = 0x24,
5971 	FMT_1                                            = 0x25,
5972 	FMT_1_REVERSED                                   = 0x26,
5973 	FMT_GB_GR                                        = 0x27,
5974 	FMT_BG_RG                                        = 0x28,
5975 	FMT_32_AS_8                                      = 0x29,
5976 	FMT_32_AS_8_8                                    = 0x2a,
5977 	FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
5978 	FMT_8_8_8                                        = 0x2c,
5979 	FMT_16_16_16                                     = 0x2d,
5980 	FMT_16_16_16_FLOAT                               = 0x2e,
5981 	FMT_4_4                                          = 0x2f,
5982 	FMT_32_32_32_FLOAT                               = 0x30,
5983 	FMT_BC1                                          = 0x31,
5984 	FMT_BC2                                          = 0x32,
5985 	FMT_BC3                                          = 0x33,
5986 	FMT_BC4                                          = 0x34,
5987 	FMT_BC5                                          = 0x35,
5988 	FMT_BC6                                          = 0x36,
5989 	FMT_BC7                                          = 0x37,
5990 	FMT_32_AS_32_32_32_32                            = 0x38,
5991 	FMT_APC3                                         = 0x39,
5992 	FMT_APC4                                         = 0x3a,
5993 	FMT_APC5                                         = 0x3b,
5994 	FMT_APC6                                         = 0x3c,
5995 	FMT_APC7                                         = 0x3d,
5996 	FMT_CTX1                                         = 0x3e,
5997 	FMT_RESERVED_63                                  = 0x3f,
5998 } SurfaceFormat;
5999 typedef enum BUF_DATA_FORMAT {
6000 	BUF_DATA_FORMAT_INVALID                          = 0x0,
6001 	BUF_DATA_FORMAT_8                                = 0x1,
6002 	BUF_DATA_FORMAT_16                               = 0x2,
6003 	BUF_DATA_FORMAT_8_8                              = 0x3,
6004 	BUF_DATA_FORMAT_32                               = 0x4,
6005 	BUF_DATA_FORMAT_16_16                            = 0x5,
6006 	BUF_DATA_FORMAT_10_11_11                         = 0x6,
6007 	BUF_DATA_FORMAT_11_11_10                         = 0x7,
6008 	BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
6009 	BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
6010 	BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
6011 	BUF_DATA_FORMAT_32_32                            = 0xb,
6012 	BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
6013 	BUF_DATA_FORMAT_32_32_32                         = 0xd,
6014 	BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
6015 	BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
6016 } BUF_DATA_FORMAT;
6017 typedef enum IMG_DATA_FORMAT {
6018 	IMG_DATA_FORMAT_INVALID                          = 0x0,
6019 	IMG_DATA_FORMAT_8                                = 0x1,
6020 	IMG_DATA_FORMAT_16                               = 0x2,
6021 	IMG_DATA_FORMAT_8_8                              = 0x3,
6022 	IMG_DATA_FORMAT_32                               = 0x4,
6023 	IMG_DATA_FORMAT_16_16                            = 0x5,
6024 	IMG_DATA_FORMAT_10_11_11                         = 0x6,
6025 	IMG_DATA_FORMAT_11_11_10                         = 0x7,
6026 	IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
6027 	IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
6028 	IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
6029 	IMG_DATA_FORMAT_32_32                            = 0xb,
6030 	IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
6031 	IMG_DATA_FORMAT_32_32_32                         = 0xd,
6032 	IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
6033 	IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
6034 	IMG_DATA_FORMAT_5_6_5                            = 0x10,
6035 	IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
6036 	IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
6037 	IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
6038 	IMG_DATA_FORMAT_8_24                             = 0x14,
6039 	IMG_DATA_FORMAT_24_8                             = 0x15,
6040 	IMG_DATA_FORMAT_X24_8_32                         = 0x16,
6041 	IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
6042 	IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
6043 	IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
6044 	IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
6045 	IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
6046 	IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
6047 	IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
6048 	IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
6049 	IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
6050 	IMG_DATA_FORMAT_GB_GR                            = 0x20,
6051 	IMG_DATA_FORMAT_BG_RG                            = 0x21,
6052 	IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
6053 	IMG_DATA_FORMAT_BC1                              = 0x23,
6054 	IMG_DATA_FORMAT_BC2                              = 0x24,
6055 	IMG_DATA_FORMAT_BC3                              = 0x25,
6056 	IMG_DATA_FORMAT_BC4                              = 0x26,
6057 	IMG_DATA_FORMAT_BC5                              = 0x27,
6058 	IMG_DATA_FORMAT_BC6                              = 0x28,
6059 	IMG_DATA_FORMAT_BC7                              = 0x29,
6060 	IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
6061 	IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
6062 	IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
6063 	IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
6064 	IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
6065 	IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
6066 	IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
6067 	IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
6068 	IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
6069 	IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
6070 	IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
6071 	IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
6072 	IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
6073 	IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
6074 	IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
6075 	IMG_DATA_FORMAT_4_4                              = 0x39,
6076 	IMG_DATA_FORMAT_6_5_5                            = 0x3a,
6077 	IMG_DATA_FORMAT_1                                = 0x3b,
6078 	IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
6079 	IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
6080 	IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
6081 	IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
6082 } IMG_DATA_FORMAT;
6083 typedef enum BUF_NUM_FORMAT {
6084 	BUF_NUM_FORMAT_UNORM                             = 0x0,
6085 	BUF_NUM_FORMAT_SNORM                             = 0x1,
6086 	BUF_NUM_FORMAT_USCALED                           = 0x2,
6087 	BUF_NUM_FORMAT_SSCALED                           = 0x3,
6088 	BUF_NUM_FORMAT_UINT                              = 0x4,
6089 	BUF_NUM_FORMAT_SINT                              = 0x5,
6090 	BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
6091 	BUF_NUM_FORMAT_FLOAT                             = 0x7,
6092 } BUF_NUM_FORMAT;
6093 typedef enum IMG_NUM_FORMAT {
6094 	IMG_NUM_FORMAT_UNORM                             = 0x0,
6095 	IMG_NUM_FORMAT_SNORM                             = 0x1,
6096 	IMG_NUM_FORMAT_USCALED                           = 0x2,
6097 	IMG_NUM_FORMAT_SSCALED                           = 0x3,
6098 	IMG_NUM_FORMAT_UINT                              = 0x4,
6099 	IMG_NUM_FORMAT_SINT                              = 0x5,
6100 	IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
6101 	IMG_NUM_FORMAT_FLOAT                             = 0x7,
6102 	IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
6103 	IMG_NUM_FORMAT_SRGB                              = 0x9,
6104 	IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
6105 	IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
6106 	IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
6107 	IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
6108 	IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
6109 	IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
6110 } IMG_NUM_FORMAT;
6111 typedef enum TileType {
6112 	ARRAY_COLOR_TILE                                 = 0x0,
6113 	ARRAY_DEPTH_TILE                                 = 0x1,
6114 } TileType;
6115 typedef enum NonDispTilingOrder {
6116 	ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
6117 	ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
6118 } NonDispTilingOrder;
6119 typedef enum MicroTileMode {
6120 	ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
6121 	ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
6122 	ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
6123 	ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
6124 	ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
6125 } MicroTileMode;
6126 typedef enum TileSplit {
6127 	ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
6128 	ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
6129 	ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
6130 	ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
6131 	ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
6132 	ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
6133 	ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
6134 } TileSplit;
6135 typedef enum SampleSplit {
6136 	ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
6137 	ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
6138 	ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
6139 	ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
6140 } SampleSplit;
6141 typedef enum PipeConfig {
6142 	ADDR_SURF_P2                                     = 0x0,
6143 	ADDR_SURF_P2_RESERVED0                           = 0x1,
6144 	ADDR_SURF_P2_RESERVED1                           = 0x2,
6145 	ADDR_SURF_P2_RESERVED2                           = 0x3,
6146 	ADDR_SURF_P4_8x16                                = 0x4,
6147 	ADDR_SURF_P4_16x16                               = 0x5,
6148 	ADDR_SURF_P4_16x32                               = 0x6,
6149 	ADDR_SURF_P4_32x32                               = 0x7,
6150 	ADDR_SURF_P8_16x16_8x16                          = 0x8,
6151 	ADDR_SURF_P8_16x32_8x16                          = 0x9,
6152 	ADDR_SURF_P8_32x32_8x16                          = 0xa,
6153 	ADDR_SURF_P8_16x32_16x16                         = 0xb,
6154 	ADDR_SURF_P8_32x32_16x16                         = 0xc,
6155 	ADDR_SURF_P8_32x32_16x32                         = 0xd,
6156 	ADDR_SURF_P8_32x64_32x32                         = 0xe,
6157 	ADDR_SURF_P8_RESERVED0                           = 0xf,
6158 	ADDR_SURF_P16_32x32_8x16                         = 0x10,
6159 	ADDR_SURF_P16_32x32_16x16                        = 0x11,
6160 } PipeConfig;
6161 typedef enum NumBanks {
6162 	ADDR_SURF_2_BANK                                 = 0x0,
6163 	ADDR_SURF_4_BANK                                 = 0x1,
6164 	ADDR_SURF_8_BANK                                 = 0x2,
6165 	ADDR_SURF_16_BANK                                = 0x3,
6166 } NumBanks;
6167 typedef enum BankWidth {
6168 	ADDR_SURF_BANK_WIDTH_1                           = 0x0,
6169 	ADDR_SURF_BANK_WIDTH_2                           = 0x1,
6170 	ADDR_SURF_BANK_WIDTH_4                           = 0x2,
6171 	ADDR_SURF_BANK_WIDTH_8                           = 0x3,
6172 } BankWidth;
6173 typedef enum BankHeight {
6174 	ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
6175 	ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
6176 	ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
6177 	ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
6178 } BankHeight;
6179 typedef enum BankWidthHeight {
6180 	ADDR_SURF_BANK_WH_1                              = 0x0,
6181 	ADDR_SURF_BANK_WH_2                              = 0x1,
6182 	ADDR_SURF_BANK_WH_4                              = 0x2,
6183 	ADDR_SURF_BANK_WH_8                              = 0x3,
6184 } BankWidthHeight;
6185 typedef enum MacroTileAspect {
6186 	ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
6187 	ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
6188 	ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
6189 	ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
6190 } MacroTileAspect;
6191 typedef enum GATCL1RequestType {
6192 	GATCL1_TYPE_NORMAL                               = 0x0,
6193 	GATCL1_TYPE_SHOOTDOWN                            = 0x1,
6194 	GATCL1_TYPE_BYPASS                               = 0x2,
6195 } GATCL1RequestType;
6196 typedef enum TCC_CACHE_POLICIES {
6197 	TCC_CACHE_POLICY_LRU                             = 0x0,
6198 	TCC_CACHE_POLICY_STREAM                          = 0x1,
6199 } TCC_CACHE_POLICIES;
6200 typedef enum MTYPE {
6201 	MTYPE_NC_NV                                      = 0x0,
6202 	MTYPE_NC                                         = 0x1,
6203 	MTYPE_CC                                         = 0x2,
6204 	MTYPE_UC                                         = 0x3,
6205 } MTYPE;
6206 typedef enum PERFMON_COUNTER_MODE {
6207 	PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
6208 	PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
6209 	PERFMON_COUNTER_MODE_MAX                         = 0x2,
6210 	PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
6211 	PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
6212 	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
6213 	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
6214 	PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
6215 	PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
6216 	PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
6217 	PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
6218 } PERFMON_COUNTER_MODE;
6219 typedef enum PERFMON_SPM_MODE {
6220 	PERFMON_SPM_MODE_OFF                             = 0x0,
6221 	PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
6222 	PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
6223 	PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
6224 	PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
6225 	PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
6226 	PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
6227 	PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
6228 	PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
6229 	PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
6230 	PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
6231 } PERFMON_SPM_MODE;
6232 typedef enum SurfaceTiling {
6233 	ARRAY_LINEAR                                     = 0x0,
6234 	ARRAY_TILED                                      = 0x1,
6235 } SurfaceTiling;
6236 typedef enum SurfaceArray {
6237 	ARRAY_1D                                         = 0x0,
6238 	ARRAY_2D                                         = 0x1,
6239 	ARRAY_3D                                         = 0x2,
6240 	ARRAY_3D_SLICE                                   = 0x3,
6241 } SurfaceArray;
6242 typedef enum ColorArray {
6243 	ARRAY_2D_ALT_COLOR                               = 0x0,
6244 	ARRAY_2D_COLOR                                   = 0x1,
6245 	ARRAY_3D_SLICE_COLOR                             = 0x3,
6246 } ColorArray;
6247 typedef enum DepthArray {
6248 	ARRAY_2D_ALT_DEPTH                               = 0x0,
6249 	ARRAY_2D_DEPTH                                   = 0x1,
6250 } DepthArray;
6251 typedef enum ENUM_NUM_SIMD_PER_CU {
6252 	NUM_SIMD_PER_CU                                  = 0x4,
6253 } ENUM_NUM_SIMD_PER_CU;
6254 typedef enum MEM_PWR_FORCE_CTRL {
6255 	NO_FORCE_REQUEST                                 = 0x0,
6256 	FORCE_LIGHT_SLEEP_REQUEST                        = 0x1,
6257 	FORCE_DEEP_SLEEP_REQUEST                         = 0x2,
6258 	FORCE_SHUT_DOWN_REQUEST                          = 0x3,
6259 } MEM_PWR_FORCE_CTRL;
6260 typedef enum MEM_PWR_FORCE_CTRL2 {
6261 	NO_FORCE_REQ                                     = 0x0,
6262 	FORCE_LIGHT_SLEEP_REQ                            = 0x1,
6263 } MEM_PWR_FORCE_CTRL2;
6264 typedef enum MEM_PWR_DIS_CTRL {
6265 	ENABLE_MEM_PWR_CTRL                              = 0x0,
6266 	DISABLE_MEM_PWR_CTRL                             = 0x1,
6267 } MEM_PWR_DIS_CTRL;
6268 typedef enum MEM_PWR_SEL_CTRL {
6269 	DYNAMIC_SHUT_DOWN_ENABLE                         = 0x0,
6270 	DYNAMIC_DEEP_SLEEP_ENABLE                        = 0x1,
6271 	DYNAMIC_LIGHT_SLEEP_ENABLE                       = 0x2,
6272 } MEM_PWR_SEL_CTRL;
6273 typedef enum MEM_PWR_SEL_CTRL2 {
6274 	DYNAMIC_DEEP_SLEEP_EN                            = 0x0,
6275 	DYNAMIC_LIGHT_SLEEP_EN                           = 0x1,
6276 } MEM_PWR_SEL_CTRL2;
6277 typedef enum HPD_INT_CONTROL_ACK {
6278 	HPD_INT_CONTROL_ACK_0                            = 0x0,
6279 	HPD_INT_CONTROL_ACK_1                            = 0x1,
6280 } HPD_INT_CONTROL_ACK;
6281 typedef enum HPD_INT_CONTROL_POLARITY {
6282 	HPD_INT_CONTROL_GEN_INT_ON_DISCON                = 0x0,
6283 	HPD_INT_CONTROL_GEN_INT_ON_CON                   = 0x1,
6284 } HPD_INT_CONTROL_POLARITY;
6285 typedef enum HPD_INT_CONTROL_RX_INT_ACK {
6286 	HPD_INT_CONTROL_RX_INT_ACK_0                     = 0x0,
6287 	HPD_INT_CONTROL_RX_INT_ACK_1                     = 0x1,
6288 } HPD_INT_CONTROL_RX_INT_ACK;
6289 typedef enum DPDBG_EN {
6290 	DPDBG_DISABLE                                    = 0x0,
6291 	DPDBG_ENABLE                                     = 0x1,
6292 } DPDBG_EN;
6293 typedef enum DPDBG_INPUT_EN {
6294 	DPDBG_INPUT_DISABLE                              = 0x0,
6295 	DPDBG_INPUT_ENABLE                               = 0x1,
6296 } DPDBG_INPUT_EN;
6297 typedef enum DPDBG_ERROR_DETECTION_MODE {
6298 	DPDBG_ERROR_DETECTION_MODE_CSC                   = 0x0,
6299 	DPDBG_ERROR_DETECTION_MODE_RS_ENCODING           = 0x1,
6300 } DPDBG_ERROR_DETECTION_MODE;
6301 typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK {
6302 	DPDBG_FIFO_OVERFLOW_INT_DISABLE                  = 0x0,
6303 	DPDBG_FIFO_OVERFLOW_INT_ENABLE                   = 0x1,
6304 } DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK;
6305 typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE {
6306 	DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED              = 0x0,
6307 	DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED              = 0x1,
6308 } DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE;
6309 typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK {
6310 	DPDBG_FIFO_OVERFLOW_INT_NO_ACK                   = 0x0,
6311 	DPDBG_FIFO_OVERFLOW_INT_CLEAR                    = 0x1,
6312 } DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK;
6313 typedef enum PM_ASSERT_RESET {
6314 	PM_ASSERT_RESET_0                                = 0x0,
6315 	PM_ASSERT_RESET_1                                = 0x1,
6316 } PM_ASSERT_RESET;
6317 typedef enum DAC_MUX_SELECT {
6318 	DAC_MUX_SELECT_DACA                              = 0x0,
6319 	DAC_MUX_SELECT_DACB                              = 0x1,
6320 } DAC_MUX_SELECT;
6321 typedef enum TMDS_DVO_MUX_SELECT {
6322 	TMDS_DVO_MUX_SELECT_B                            = 0x0,
6323 	TMDS_DVO_MUX_SELECT_G                            = 0x1,
6324 	TMDS_DVO_MUX_SELECT_R                            = 0x2,
6325 	TMDS_DVO_MUX_SELECT_RESERVED                     = 0x3,
6326 } TMDS_DVO_MUX_SELECT;
6327 typedef enum DACA_SOFT_RESET {
6328 	DACA_SOFT_RESET_0                                = 0x0,
6329 	DACA_SOFT_RESET_1                                = 0x1,
6330 } DACA_SOFT_RESET;
6331 typedef enum I2S0_SPDIF0_SOFT_RESET {
6332 	I2S0_SPDIF0_SOFT_RESET_0                         = 0x0,
6333 	I2S0_SPDIF0_SOFT_RESET_1                         = 0x1,
6334 } I2S0_SPDIF0_SOFT_RESET;
6335 typedef enum I2S1_SOFT_RESET {
6336 	I2S1_SOFT_RESET_0                                = 0x0,
6337 	I2S1_SOFT_RESET_1                                = 0x1,
6338 } I2S1_SOFT_RESET;
6339 typedef enum SPDIF1_SOFT_RESET {
6340 	SPDIF1_SOFT_RESET_0                              = 0x0,
6341 	SPDIF1_SOFT_RESET_1                              = 0x1,
6342 } SPDIF1_SOFT_RESET;
6343 typedef enum DB_CLK_SOFT_RESET {
6344 	DB_CLK_SOFT_RESET_0                              = 0x0,
6345 	DB_CLK_SOFT_RESET_1                              = 0x1,
6346 } DB_CLK_SOFT_RESET;
6347 typedef enum FMT0_SOFT_RESET {
6348 	FMT0_SOFT_RESET_0                                = 0x0,
6349 	FMT0_SOFT_RESET_1                                = 0x1,
6350 } FMT0_SOFT_RESET;
6351 typedef enum FMT1_SOFT_RESET {
6352 	FMT1_SOFT_RESET_0                                = 0x0,
6353 	FMT1_SOFT_RESET_1                                = 0x1,
6354 } FMT1_SOFT_RESET;
6355 typedef enum FMT2_SOFT_RESET {
6356 	FMT2_SOFT_RESET_0                                = 0x0,
6357 	FMT2_SOFT_RESET_1                                = 0x1,
6358 } FMT2_SOFT_RESET;
6359 typedef enum FMT3_SOFT_RESET {
6360 	FMT3_SOFT_RESET_0                                = 0x0,
6361 	FMT3_SOFT_RESET_1                                = 0x1,
6362 } FMT3_SOFT_RESET;
6363 typedef enum FMT4_SOFT_RESET {
6364 	FMT4_SOFT_RESET_0                                = 0x0,
6365 	FMT4_SOFT_RESET_1                                = 0x1,
6366 } FMT4_SOFT_RESET;
6367 typedef enum FMT5_SOFT_RESET {
6368 	FMT5_SOFT_RESET_0                                = 0x0,
6369 	FMT5_SOFT_RESET_1                                = 0x1,
6370 } FMT5_SOFT_RESET;
6371 typedef enum MVP_SOFT_RESET {
6372 	MVP_SOFT_RESET_0                                 = 0x0,
6373 	MVP_SOFT_RESET_1                                 = 0x1,
6374 } MVP_SOFT_RESET;
6375 typedef enum ABM_SOFT_RESET {
6376 	ABM_SOFT_RESET_0                                 = 0x0,
6377 	ABM_SOFT_RESET_1                                 = 0x1,
6378 } ABM_SOFT_RESET;
6379 typedef enum DVO_SOFT_RESET {
6380 	DVO_SOFT_RESET_0                                 = 0x0,
6381 	DVO_SOFT_RESET_1                                 = 0x1,
6382 } DVO_SOFT_RESET;
6383 typedef enum DIGA_FE_SOFT_RESET {
6384 	DIGA_FE_SOFT_RESET_0                             = 0x0,
6385 	DIGA_FE_SOFT_RESET_1                             = 0x1,
6386 } DIGA_FE_SOFT_RESET;
6387 typedef enum DIGA_BE_SOFT_RESET {
6388 	DIGA_BE_SOFT_RESET_0                             = 0x0,
6389 	DIGA_BE_SOFT_RESET_1                             = 0x1,
6390 } DIGA_BE_SOFT_RESET;
6391 typedef enum DIGB_FE_SOFT_RESET {
6392 	DIGB_FE_SOFT_RESET_0                             = 0x0,
6393 	DIGB_FE_SOFT_RESET_1                             = 0x1,
6394 } DIGB_FE_SOFT_RESET;
6395 typedef enum DIGB_BE_SOFT_RESET {
6396 	DIGB_BE_SOFT_RESET_0                             = 0x0,
6397 	DIGB_BE_SOFT_RESET_1                             = 0x1,
6398 } DIGB_BE_SOFT_RESET;
6399 typedef enum DIGC_FE_SOFT_RESET {
6400 	DIGC_FE_SOFT_RESET_0                             = 0x0,
6401 	DIGC_FE_SOFT_RESET_1                             = 0x1,
6402 } DIGC_FE_SOFT_RESET;
6403 typedef enum DIGC_BE_SOFT_RESET {
6404 	DIGC_BE_SOFT_RESET_0                             = 0x0,
6405 	DIGC_BE_SOFT_RESET_1                             = 0x1,
6406 } DIGC_BE_SOFT_RESET;
6407 typedef enum DIGD_FE_SOFT_RESET {
6408 	DIGD_FE_SOFT_RESET_0                             = 0x0,
6409 	DIGD_FE_SOFT_RESET_1                             = 0x1,
6410 } DIGD_FE_SOFT_RESET;
6411 typedef enum DIGD_BE_SOFT_RESET {
6412 	DIGD_BE_SOFT_RESET_0                             = 0x0,
6413 	DIGD_BE_SOFT_RESET_1                             = 0x1,
6414 } DIGD_BE_SOFT_RESET;
6415 typedef enum DIGE_FE_SOFT_RESET {
6416 	DIGE_FE_SOFT_RESET_0                             = 0x0,
6417 	DIGE_FE_SOFT_RESET_1                             = 0x1,
6418 } DIGE_FE_SOFT_RESET;
6419 typedef enum DIGE_BE_SOFT_RESET {
6420 	DIGE_BE_SOFT_RESET_0                             = 0x0,
6421 	DIGE_BE_SOFT_RESET_1                             = 0x1,
6422 } DIGE_BE_SOFT_RESET;
6423 typedef enum DIGF_FE_SOFT_RESET {
6424 	DIGF_FE_SOFT_RESET_0                             = 0x0,
6425 	DIGF_FE_SOFT_RESET_1                             = 0x1,
6426 } DIGF_FE_SOFT_RESET;
6427 typedef enum DIGF_BE_SOFT_RESET {
6428 	DIGF_BE_SOFT_RESET_0                             = 0x0,
6429 	DIGF_BE_SOFT_RESET_1                             = 0x1,
6430 } DIGF_BE_SOFT_RESET;
6431 typedef enum DIGG_FE_SOFT_RESET {
6432 	DIGG_FE_SOFT_RESET_0                             = 0x0,
6433 	DIGG_FE_SOFT_RESET_1                             = 0x1,
6434 } DIGG_FE_SOFT_RESET;
6435 typedef enum DIGG_BE_SOFT_RESET {
6436 	DIGG_BE_SOFT_RESET_0                             = 0x0,
6437 	DIGG_BE_SOFT_RESET_1                             = 0x1,
6438 } DIGG_BE_SOFT_RESET;
6439 typedef enum DPDBG_SOFT_RESET {
6440 	DPDBG_SOFT_RESET_0                               = 0x0,
6441 	DPDBG_SOFT_RESET_1                               = 0x1,
6442 } DPDBG_SOFT_RESET;
6443 typedef enum DIGLPA_FE_SOFT_RESET {
6444 	DIGLPA_FE_SOFT_RESET_0                           = 0x0,
6445 	DIGLPA_FE_SOFT_RESET_1                           = 0x1,
6446 } DIGLPA_FE_SOFT_RESET;
6447 typedef enum DIGLPA_BE_SOFT_RESET {
6448 	DIGLPA_BE_SOFT_RESET_0                           = 0x0,
6449 	DIGLPA_BE_SOFT_RESET_1                           = 0x1,
6450 } DIGLPA_BE_SOFT_RESET;
6451 typedef enum DIGLPB_FE_SOFT_RESET {
6452 	DIGLPB_FE_SOFT_RESET_0                           = 0x0,
6453 	DIGLPB_FE_SOFT_RESET_1                           = 0x1,
6454 } DIGLPB_FE_SOFT_RESET;
6455 typedef enum DIGLPB_BE_SOFT_RESET {
6456 	DIGLPB_BE_SOFT_RESET_0                           = 0x0,
6457 	DIGLPB_BE_SOFT_RESET_1                           = 0x1,
6458 } DIGLPB_BE_SOFT_RESET;
6459 typedef enum GENERICA_STEREOSYNC_SEL {
6460 	GENERICA_STEREOSYNC_SEL_D1                       = 0x0,
6461 	GENERICA_STEREOSYNC_SEL_D2                       = 0x1,
6462 	GENERICA_STEREOSYNC_SEL_D3                       = 0x2,
6463 	GENERICA_STEREOSYNC_SEL_D4                       = 0x3,
6464 	GENERICA_STEREOSYNC_SEL_D5                       = 0x4,
6465 	GENERICA_STEREOSYNC_SEL_D6                       = 0x5,
6466 	GENERICA_STEREOSYNC_SEL_RESERVED                 = 0x6,
6467 } GENERICA_STEREOSYNC_SEL;
6468 typedef enum GENERICB_STEREOSYNC_SEL {
6469 	GENERICB_STEREOSYNC_SEL_D1                       = 0x0,
6470 	GENERICB_STEREOSYNC_SEL_D2                       = 0x1,
6471 	GENERICB_STEREOSYNC_SEL_D3                       = 0x2,
6472 	GENERICB_STEREOSYNC_SEL_D4                       = 0x3,
6473 	GENERICB_STEREOSYNC_SEL_D5                       = 0x4,
6474 	GENERICB_STEREOSYNC_SEL_D6                       = 0x5,
6475 	GENERICB_STEREOSYNC_SEL_RESERVED                 = 0x6,
6476 } GENERICB_STEREOSYNC_SEL;
6477 typedef enum DCO_DBG_BLOCK_SEL {
6478 	DCO_DBG_BLOCK_SEL_DCO                            = 0x0,
6479 	DCO_DBG_BLOCK_SEL_ABM                            = 0x1,
6480 	DCO_DBG_BLOCK_SEL_DVO                            = 0x2,
6481 	DCO_DBG_BLOCK_SEL_DAC                            = 0x3,
6482 	DCO_DBG_BLOCK_SEL_MVP                            = 0x4,
6483 	DCO_DBG_BLOCK_SEL_FMT0                           = 0x5,
6484 	DCO_DBG_BLOCK_SEL_FMT1                           = 0x6,
6485 	DCO_DBG_BLOCK_SEL_FMT2                           = 0x7,
6486 	DCO_DBG_BLOCK_SEL_FMT3                           = 0x8,
6487 	DCO_DBG_BLOCK_SEL_FMT4                           = 0x9,
6488 	DCO_DBG_BLOCK_SEL_FMT5                           = 0xa,
6489 	DCO_DBG_BLOCK_SEL_DIGFE_A                        = 0xb,
6490 	DCO_DBG_BLOCK_SEL_DIGFE_B                        = 0xc,
6491 	DCO_DBG_BLOCK_SEL_DIGFE_C                        = 0xd,
6492 	DCO_DBG_BLOCK_SEL_DIGFE_D                        = 0xe,
6493 	DCO_DBG_BLOCK_SEL_DIGFE_E                        = 0xf,
6494 	DCO_DBG_BLOCK_SEL_DIGFE_F                        = 0x10,
6495 	DCO_DBG_BLOCK_SEL_DIGFE_G                        = 0x11,
6496 	DCO_DBG_BLOCK_SEL_DIGA                           = 0x12,
6497 	DCO_DBG_BLOCK_SEL_DIGB                           = 0x13,
6498 	DCO_DBG_BLOCK_SEL_DIGC                           = 0x14,
6499 	DCO_DBG_BLOCK_SEL_DIGD                           = 0x15,
6500 	DCO_DBG_BLOCK_SEL_DIGE                           = 0x16,
6501 	DCO_DBG_BLOCK_SEL_DIGF                           = 0x17,
6502 	DCO_DBG_BLOCK_SEL_DIGG                           = 0x18,
6503 	DCO_DBG_BLOCK_SEL_DPFE_A                         = 0x19,
6504 	DCO_DBG_BLOCK_SEL_DPFE_B                         = 0x1a,
6505 	DCO_DBG_BLOCK_SEL_DPFE_C                         = 0x1b,
6506 	DCO_DBG_BLOCK_SEL_DPFE_D                         = 0x1c,
6507 	DCO_DBG_BLOCK_SEL_DPFE_E                         = 0x1d,
6508 	DCO_DBG_BLOCK_SEL_DPFE_F                         = 0x1e,
6509 	DCO_DBG_BLOCK_SEL_DPFE_G                         = 0x1f,
6510 	DCO_DBG_BLOCK_SEL_DPA                            = 0x20,
6511 	DCO_DBG_BLOCK_SEL_DPB                            = 0x21,
6512 	DCO_DBG_BLOCK_SEL_DPC                            = 0x22,
6513 	DCO_DBG_BLOCK_SEL_DPD                            = 0x23,
6514 	DCO_DBG_BLOCK_SEL_DPE                            = 0x24,
6515 	DCO_DBG_BLOCK_SEL_DPF                            = 0x25,
6516 	DCO_DBG_BLOCK_SEL_DPG                            = 0x26,
6517 	DCO_DBG_BLOCK_SEL_AUX0                           = 0x27,
6518 	DCO_DBG_BLOCK_SEL_AUX1                           = 0x28,
6519 	DCO_DBG_BLOCK_SEL_AUX2                           = 0x29,
6520 	DCO_DBG_BLOCK_SEL_AUX3                           = 0x2a,
6521 	DCO_DBG_BLOCK_SEL_AUX4                           = 0x2b,
6522 	DCO_DBG_BLOCK_SEL_AUX5                           = 0x2c,
6523 	DCO_DBG_BLOCK_SEL_PERFMON_DCO                    = 0x2d,
6524 	DCO_DBG_BLOCK_SEL_AUDIO_OUT                      = 0x2e,
6525 	DCO_DBG_BLOCK_SEL_DIGLPFEA                       = 0x2f,
6526 	DCO_DBG_BLOCK_SEL_DIGLPFEB                       = 0x30,
6527 	DCO_DBG_BLOCK_SEL_DIGLPA                         = 0x31,
6528 	DCO_DBG_BLOCK_SEL_DIGLPB                         = 0x32,
6529 	DCO_DBG_BLOCK_SEL_DPLPFEA                        = 0x33,
6530 	DCO_DBG_BLOCK_SEL_DPLPFEB                        = 0x34,
6531 	DCO_DBG_BLOCK_SEL_DPLPA                          = 0x35,
6532 	DCO_DBG_BLOCK_SEL_DPLPB                          = 0x36,
6533 } DCO_DBG_BLOCK_SEL;
6534 typedef enum DCO_DBG_CLOCK_SEL {
6535 	DCO_DBG_CLOCK_SEL_DISPCLK                        = 0x0,
6536 	DCO_DBG_CLOCK_SEL_SCLK                           = 0x1,
6537 	DCO_DBG_CLOCK_SEL_MVPCLK                         = 0x2,
6538 	DCO_DBG_CLOCK_SEL_DVOCLK                         = 0x3,
6539 	DCO_DBG_CLOCK_SEL_DACCLK                         = 0x4,
6540 	DCO_DBG_CLOCK_SEL_REFCLK                         = 0x5,
6541 	DCO_DBG_CLOCK_SEL_SYMCLKA                        = 0x6,
6542 	DCO_DBG_CLOCK_SEL_SYMCLKB                        = 0x7,
6543 	DCO_DBG_CLOCK_SEL_SYMCLKC                        = 0x8,
6544 	DCO_DBG_CLOCK_SEL_SYMCLKD                        = 0x9,
6545 	DCO_DBG_CLOCK_SEL_SYMCLKE                        = 0xa,
6546 	DCO_DBG_CLOCK_SEL_SYMCLKF                        = 0xb,
6547 	DCO_DBG_CLOCK_SEL_SYMCLKG                        = 0xc,
6548 	DCO_DBG_CLOCK_SEL_RESERVED                       = 0xd,
6549 	DCO_DBG_CLOCK_SEL_AM0CLK                         = 0xe,
6550 	DCO_DBG_CLOCK_SEL_AM1CLK                         = 0xf,
6551 	DCO_DBG_CLOCK_SEL_AM2CLK                         = 0x10,
6552 	DCO_DBG_CLOCK_SEL_SYMCLKLPA                      = 0x11,
6553 	DCO_DBG_CLOCK_SEL_SYMCLKLPB                      = 0x12,
6554 } DCO_DBG_CLOCK_SEL;
6555 typedef enum DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE {
6556 	DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL               = 0x0,
6557 	DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE               = 0x1,
6558 } DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE;
6559 typedef enum FMT420_MEMORY_SOURCE_SEL {
6560 	FMT420_MEMORY_SOURCE_SEL_FMT0                    = 0x0,
6561 	FMT420_MEMORY_SOURCE_SEL_FMT1                    = 0x1,
6562 	FMT420_MEMORY_SOURCE_SEL_FMT2                    = 0x2,
6563 	FMT420_MEMORY_SOURCE_SEL_FMT3                    = 0x3,
6564 	FMT420_MEMORY_SOURCE_SEL_FMT4                    = 0x4,
6565 	FMT420_MEMORY_SOURCE_SEL_FMT5                    = 0x5,
6566 	FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED            = 0x6,
6567 } FMT420_MEMORY_SOURCE_SEL;
6568 typedef enum DOUT_I2C_CONTROL_GO {
6569 	DOUT_I2C_CONTROL_STOP_TRANSFER                   = 0x0,
6570 	DOUT_I2C_CONTROL_START_TRANSFER                  = 0x1,
6571 } DOUT_I2C_CONTROL_GO;
6572 typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
6573 	DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER        = 0x0,
6574 	DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER            = 0x1,
6575 } DOUT_I2C_CONTROL_SOFT_RESET;
6576 typedef enum DOUT_I2C_CONTROL_SEND_RESET {
6577 	DOUT_I2C_CONTROL__NOT_SEND_RESET                 = 0x0,
6578 	DOUT_I2C_CONTROL__SEND_RESET                     = 0x1,
6579 } DOUT_I2C_CONTROL_SEND_RESET;
6580 typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
6581 	DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS             = 0x0,
6582 	DOUT_I2C_CONTROL_RESET_SW_STATUS                 = 0x1,
6583 } DOUT_I2C_CONTROL_SW_STATUS_RESET;
6584 typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
6585 	DOUT_I2C_CONTROL_SELECT_DDC1                     = 0x0,
6586 	DOUT_I2C_CONTROL_SELECT_DDC2                     = 0x1,
6587 	DOUT_I2C_CONTROL_SELECT_DDC3                     = 0x2,
6588 	DOUT_I2C_CONTROL_SELECT_DDC4                     = 0x3,
6589 	DOUT_I2C_CONTROL_SELECT_DDC5                     = 0x4,
6590 	DOUT_I2C_CONTROL_SELECT_DDC6                     = 0x5,
6591 	DOUT_I2C_CONTROL_SELECT_DDCVGA                   = 0x6,
6592 } DOUT_I2C_CONTROL_DDC_SELECT;
6593 typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
6594 	DOUT_I2C_CONTROL_TRANS0                          = 0x0,
6595 	DOUT_I2C_CONTROL_TRANS0_TRANS1                   = 0x1,
6596 	DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2            = 0x2,
6597 	DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3     = 0x3,
6598 } DOUT_I2C_CONTROL_TRANSACTION_COUNT;
6599 typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL {
6600 	DOUT_I2C_CONTROL_NORMAL_DEBUG                    = 0x0,
6601 	DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG            = 0x1,
6602 } DOUT_I2C_CONTROL_DBG_REF_SEL;
6603 typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
6604 	DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL          = 0x0,
6605 	DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH            = 0x1,
6606 	DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED      = 0x2,
6607 	DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED      = 0x3,
6608 } DOUT_I2C_ARBITRATION_SW_PRIORITY;
6609 typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
6610 	DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED            = 0x0,
6611 	DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED           = 0x1,
6612 } DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO;
6613 typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
6614 	DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER  = 0x0,
6615 	DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER      = 0x1,
6616 } DOUT_I2C_ARBITRATION_ABORT_XFER;
6617 typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
6618 	DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ        = 0x0,
6619 	DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ            = 0x1,
6620 } DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ;
6621 typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
6622 	DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG     = 0x0,
6623 	DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG         = 0x1,
6624 } DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG;
6625 typedef enum DOUT_I2C_ACK {
6626 	DOUT_I2C_NO_ACK                                  = 0x0,
6627 	DOUT_I2C_ACK_TO_CLEAN                            = 0x1,
6628 } DOUT_I2C_ACK;
6629 typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
6630 	DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO       = 0x0,
6631 	DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE= 0x1,
6632 	DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE= 0x2,
6633 	DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE= 0x3,
6634 } DOUT_I2C_DDC_SPEED_THRESHOLD;
6635 typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
6636 	DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR= 0x0,
6637 	DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA             = 0x1,
6638 } DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN;
6639 typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
6640 	DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS        = 0x0,
6641 	DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS        = 0x1,
6642 } DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL;
6643 typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
6644 	DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT           = 0x0,
6645 	DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT        = 0x1,
6646 } DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE;
6647 typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
6648 	DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR= 0x0,
6649 	DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL             = 0x1,
6650 } DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN;
6651 typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
6652 	DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS          = 0x0,
6653 	DOUT_I2C_TRANSACTION_STOP_ALL_TRANS              = 0x1,
6654 } DOUT_I2C_TRANSACTION_STOP_ON_NACK;
6655 typedef enum DOUT_I2C_DATA_INDEX_WRITE {
6656 	DOUT_I2C_DATA__NOT_INDEX_WRITE                   = 0x0,
6657 	DOUT_I2C_DATA__INDEX_WRITE                       = 0x1,
6658 } DOUT_I2C_DATA_INDEX_WRITE;
6659 typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
6660 	DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION= 0x0,
6661 	DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION= 0x1,
6662 } DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET;
6663 typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
6664 	DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL      = 0x0,
6665 	DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE      = 0x1,
6666 } DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE;
6667 typedef enum BLNDV_CONTROL_BLND_MODE {
6668 	BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY        = 0x0,
6669 	BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY          = 0x1,
6670 	BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE      = 0x2,
6671 	BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE        = 0x3,
6672 } BLNDV_CONTROL_BLND_MODE;
6673 typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE {
6674 	BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO= 0x0,
6675 	BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO= 0x1,
6676 	BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2,
6677 	BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED            = 0x3,
6678 } BLNDV_CONTROL_BLND_STEREO_TYPE;
6679 typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY {
6680 	BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW           = 0x0,
6681 	BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH          = 0x1,
6682 } BLNDV_CONTROL_BLND_STEREO_POLARITY;
6683 typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN {
6684 	BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE          = 0x0,
6685 	BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE           = 0x1,
6686 } BLNDV_CONTROL_BLND_FEEDTHROUGH_EN;
6687 typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE {
6688 	BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA= 0x0,
6689 	BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN= 0x1,
6690 	BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY  = 0x2,
6691 	BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED             = 0x3,
6692 } BLNDV_CONTROL_BLND_ALPHA_MODE;
6693 typedef enum BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
6694 	BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE     = 0x0,
6695 	BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE      = 0x1,
6696 } BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY;
6697 typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE {
6698 	BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE         = 0x0,
6699 	BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE          = 0x1,
6700 } BLNDV_CONTROL_BLND_MULTIPLIED_MODE;
6701 typedef enum BLNDV_SM_CONTROL2_SM_MODE {
6702 	BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE           = 0x0,
6703 	BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING        = 0x2,
6704 	BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING     = 0x4,
6705 	BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING= 0x6,
6706 } BLNDV_SM_CONTROL2_SM_MODE;
6707 typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE {
6708 	BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE       = 0x0,
6709 	BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE        = 0x1,
6710 } BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE;
6711 typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE {
6712 	BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE       = 0x0,
6713 	BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE        = 0x1,
6714 } BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE;
6715 typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
6716 	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE= 0x0,
6717 	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED= 0x1,
6718 	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2,
6719 	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH= 0x3,
6720 } BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
6721 typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
6722 	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x0,
6723 	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x1,
6724 	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW= 0x2,
6725 	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH= 0x3,
6726 } BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
6727 typedef enum BLNDV_CONTROL2_PTI_ENABLE {
6728 	BLNDV_CONTROL2_PTI_ENABLE_FALSE                  = 0x0,
6729 	BLNDV_CONTROL2_PTI_ENABLE_TRUE                   = 0x1,
6730 } BLNDV_CONTROL2_PTI_ENABLE;
6731 typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
6732 	BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE     = 0x0,
6733 	BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE      = 0x1,
6734 } BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
6735 typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
6736 	BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE     = 0x0,
6737 	BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE      = 0x1,
6738 } BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
6739 typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
6740 	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE= 0x0,
6741 	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE= 0x1,
6742 } BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
6743 typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
6744 	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE= 0x0,
6745 	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE= 0x1,
6746 } BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
6747 typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
6748 	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE= 0x0,
6749 	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE= 0x1,
6750 } BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
6751 typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
6752 	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE= 0x0,
6753 	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE= 0x1,
6754 } BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
6755 typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
6756 	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE= 0x0,
6757 	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE= 0x1,
6758 } BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
6759 typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
6760 	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE= 0x0,
6761 	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE= 0x1,
6762 } BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
6763 typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
6764 	BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x0,
6765 	BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE  = 0x1,
6766 } BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
6767 typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
6768 	BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE= 0x0,
6769 	BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x1,
6770 } BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
6771 typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
6772 	BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE= 0x0,
6773 	BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x1,
6774 } BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
6775 typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT {
6776 	BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW              = 0x0,
6777 	BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH             = 0x1,
6778 } BLNDV_DEBUG_BLND_CNV_MUX_SELECT;
6779 typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
6780 	BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE= 0x0,
6781 	BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE= 0x1,
6782 } BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
6783 typedef enum DPCSTX_DBG_CFGCLK_SEL {
6784 	DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF                = 0x0,
6785 	DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF              = 0x1,
6786 	DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE                 = 0x2,
6787 	DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER                = 0x3,
6788 } DPCSTX_DBG_CFGCLK_SEL;
6789 typedef enum DPCSTX_TX_SYMCLK_SEL {
6790 	DPCSTX_DBG_TX_SYMCLK_SEL_IN0                     = 0x0,
6791 	DPCSTX_DBG_TX_SYMCLK_SEL_IN1                     = 0x1,
6792 	DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR                 = 0x2,
6793 } DPCSTX_TX_SYMCLK_SEL;
6794 typedef enum DPCSTX_TX_SYMCLK_DIV2_SEL {
6795 	DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0               = 0x0,
6796 	DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1               = 0x1,
6797 	DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2               = 0x2,
6798 	DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3               = 0x3,
6799 	DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD            = 0x4,
6800 	DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT                = 0x5,
6801 } DPCSTX_TX_SYMCLK_DIV2_SEL;
6802 typedef enum DPCSTX_DBG_CLOCK_SEL {
6803 	DPCSTX_DBG_CLOCK_SEL_DC_CFGCLK                   = 0x0,
6804 	DPCSTX_DBG_CLOCK_SEL_PHY_CFGCLK                  = 0x1,
6805 	DPCSTX_DBG_CLOCK_SEL_TXSYMCLK                    = 0x2,
6806 } DPCSTX_DBG_CLOCK_SEL;
6807 typedef enum DPCSTX_DVI_LINK_MODE {
6808 	DPCSTX_DVI_LINK_MODE_NORMAL                      = 0x0,
6809 	DPCSTX_DVI_LINK_MODE_DUAL_LINK_MASTER            = 0x1,
6810 	DPCSTX_DVI_LINK_MODE_DUAL_LINK_SLAVER            = 0x2,
6811 } DPCSTX_DVI_LINK_MODE;
6812 
6813 #endif /* DCE_11_2_ENUM_H */
6814