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Searched refs:CurrentChannelBW (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/staging/rtl8723bs/hal/
H A Drtl8723b_phycfg.c546 pHalData->CurrentChannelBW, in PHY_GetTxPowerIndex()
610 if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) { in phy_GetSecondaryChnl_8723B()
627 phy_SetRegBW_8723B(Adapter, pHalData->CurrentChannelBW); in phy_PostSetBwMode8723B()
636 switch (pHalData->CurrentChannelBW) { in phy_PostSetBwMode8723B()
664 PHY_RF6052SetBandwidth8723B(Adapter, pHalData->CurrentChannelBW); in phy_PostSetBwMode8723B()
713 enum channel_width tmpBW = pHalData->CurrentChannelBW; in PHY_HandleSwChnlAndSetBW8723B()
744 pHalData->CurrentChannelBW = ChnlWidth; in PHY_HandleSwChnlAndSetBW8723B()
760 pHalData->CurrentChannelBW = tmpBW; in PHY_HandleSwChnlAndSetBW8723B()
H A Dhal_com_phycfg.c431 pHalData->CurrentChannelBW, in PHY_SetTxPowerIndexByRateSection()
438 pHalData->CurrentChannelBW, in PHY_SetTxPowerIndexByRateSection()
445 pHalData->CurrentChannelBW, in PHY_SetTxPowerIndexByRateSection()
H A Drtl8723b_dm.c96 ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_BW, &(pHalData->CurrentChannelBW)); in Update_ODM_ComInfo_8723b()
H A Dhal_btcoex.c359 else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_20) in halbtcoutsrc_Get()
H A Drtl8723b_hal_init.c2466 if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) { in BWMapping_8723B()
2485 if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) { in SCMapping_8723B()
/openbmc/linux/drivers/staging/rtl8192u/
H A Dr819xU_phy.c1381 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"); in rtl8192_SetBWModeWorkItem()
1391 switch (priv->CurrentChannelBW) { in rtl8192_SetBWModeWorkItem()
1407 priv->CurrentChannelBW); in rtl8192_SetBWModeWorkItem()
1412 switch (priv->CurrentChannelBW) { in rtl8192_SetBWModeWorkItem()
1477 priv->CurrentChannelBW); in rtl8192_SetBWModeWorkItem()
1490 phy_set_rf8256_bandwidth(dev, priv->CurrentChannelBW); in rtl8192_SetBWModeWorkItem()
1529 priv->CurrentChannelBW = bandwidth; in rtl8192_SetBWMode()
H A Dr8192U_dm.c286 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { in dm_check_rate_adaptive()
307 LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ? in dm_check_rate_adaptive()
560 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) in dm_TXPowerTrackingCallback_TSSI()
673 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) /* 40M */ in dm_TXPowerTrackingCallback_ThermalMeter()
1675 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { in dm_ctrl_initgain_byrssi_by_fwfalse_alarm()
1724 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { in dm_ctrl_initgain_byrssi_by_fwfalse_alarm()
1782 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { in dm_ctrl_initgain_byrssi_highpwr()
1795 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { in dm_ctrl_initgain_byrssi_highpwr()
1906 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { in dm_pd_th()
1915 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { in dm_pd_th()
[all …]
H A Dr8192U_core.c1280 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) { in rtl8192_tx()
2744 …((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20 && priv->undecorated_smoothed_pwdb >= RATE_ADAPTIV… in HalRxCheckStuck819xUsb()
2745 …(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 && priv->undecorated_smoothed_pwdb >= RATE_ADAPTIVE… in HalRxCheckStuck819xUsb()
2750 …} else if (((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20 && priv->undecorated_smoothed_pwdb < RA… in HalRxCheckStuck819xUsb()
2751 …(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 && priv->undecorated_smoothed_pwdb < RATE_ADAPTIVE_… in HalRxCheckStuck819xUsb()
H A Dr8192U.h956 enum ht_channel_width CurrentChannelBW; member
/openbmc/linux/drivers/staging/rtl8723bs/include/
H A Dhal_data.h177 enum channel_width CurrentChannelBW; member