1 /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 2 /* 3 * Copyright(c) 2015 - 2020 Intel Corporation. 4 */ 5 6 #ifndef _CHIP_H 7 #define _CHIP_H 8 /* 9 * This file contains all of the defines that is specific to the HFI chip 10 */ 11 12 /* sizes */ 13 #define BITS_PER_REGISTER (BITS_PER_BYTE * sizeof(u64)) 14 #define NUM_INTERRUPT_SOURCES 768 15 #define RXE_NUM_CONTEXTS 160 16 #define RXE_PER_CONTEXT_SIZE 0x1000 /* 4k */ 17 #define RXE_NUM_TID_FLOWS 32 18 #define RXE_NUM_DATA_VL 8 19 #define TXE_NUM_CONTEXTS 160 20 #define TXE_NUM_SDMA_ENGINES 16 21 #define NUM_CONTEXTS_PER_SET 8 22 #define VL_ARB_HIGH_PRIO_TABLE_SIZE 16 23 #define VL_ARB_LOW_PRIO_TABLE_SIZE 16 24 #define VL_ARB_TABLE_SIZE 16 25 #define TXE_NUM_32_BIT_COUNTER 7 26 #define TXE_NUM_64_BIT_COUNTER 30 27 #define TXE_NUM_DATA_VL 8 28 #define TXE_PIO_SIZE (32 * 0x100000) /* 32 MB */ 29 #define PIO_BLOCK_SIZE 64 /* bytes */ 30 #define SDMA_BLOCK_SIZE 64 /* bytes */ 31 #define RCV_BUF_BLOCK_SIZE 64 /* bytes */ 32 #define PIO_CMASK 0x7ff /* counter mask for free and fill counters */ 33 #define MAX_EAGER_ENTRIES 2048 /* max receive eager entries */ 34 #define MAX_TID_PAIR_ENTRIES 1024 /* max receive expected pairs */ 35 /* 36 * Virtual? Allocation Unit, defined as AU = 8*2^vAU, 64 bytes, AU is fixed 37 * at 64 bytes for all generation one devices 38 */ 39 #define CM_VAU 3 40 /* HFI link credit count, AKA receive buffer depth (RBUF_DEPTH) */ 41 #define CM_GLOBAL_CREDITS 0x880 42 /* Number of PKey entries in the HW */ 43 #define MAX_PKEY_VALUES 16 44 45 #include "chip_registers.h" 46 47 #define RXE_PER_CONTEXT_USER (RXE + RXE_PER_CONTEXT_OFFSET) 48 #define TXE_PIO_SEND (TXE + TXE_PIO_SEND_OFFSET) 49 50 /* PBC flags */ 51 #define PBC_INTR BIT_ULL(31) 52 #define PBC_DC_INFO_SHIFT (30) 53 #define PBC_DC_INFO BIT_ULL(PBC_DC_INFO_SHIFT) 54 #define PBC_TEST_EBP BIT_ULL(29) 55 #define PBC_PACKET_BYPASS BIT_ULL(28) 56 #define PBC_CREDIT_RETURN BIT_ULL(25) 57 #define PBC_INSERT_BYPASS_ICRC BIT_ULL(24) 58 #define PBC_TEST_BAD_ICRC BIT_ULL(23) 59 #define PBC_FECN BIT_ULL(22) 60 61 /* PbcInsertHcrc field settings */ 62 #define PBC_IHCRC_LKDETH 0x0 /* insert @ local KDETH offset */ 63 #define PBC_IHCRC_GKDETH 0x1 /* insert @ global KDETH offset */ 64 #define PBC_IHCRC_NONE 0x2 /* no HCRC inserted */ 65 66 /* PBC fields */ 67 #define PBC_STATIC_RATE_CONTROL_COUNT_SHIFT 32 68 #define PBC_STATIC_RATE_CONTROL_COUNT_MASK 0xffffull 69 #define PBC_STATIC_RATE_CONTROL_COUNT_SMASK \ 70 (PBC_STATIC_RATE_CONTROL_COUNT_MASK << \ 71 PBC_STATIC_RATE_CONTROL_COUNT_SHIFT) 72 73 #define PBC_INSERT_HCRC_SHIFT 26 74 #define PBC_INSERT_HCRC_MASK 0x3ull 75 #define PBC_INSERT_HCRC_SMASK \ 76 (PBC_INSERT_HCRC_MASK << PBC_INSERT_HCRC_SHIFT) 77 78 #define PBC_VL_SHIFT 12 79 #define PBC_VL_MASK 0xfull 80 #define PBC_VL_SMASK (PBC_VL_MASK << PBC_VL_SHIFT) 81 82 #define PBC_LENGTH_DWS_SHIFT 0 83 #define PBC_LENGTH_DWS_MASK 0xfffull 84 #define PBC_LENGTH_DWS_SMASK \ 85 (PBC_LENGTH_DWS_MASK << PBC_LENGTH_DWS_SHIFT) 86 87 /* Credit Return Fields */ 88 #define CR_COUNTER_SHIFT 0 89 #define CR_COUNTER_MASK 0x7ffull 90 #define CR_COUNTER_SMASK (CR_COUNTER_MASK << CR_COUNTER_SHIFT) 91 92 #define CR_STATUS_SHIFT 11 93 #define CR_STATUS_MASK 0x1ull 94 #define CR_STATUS_SMASK (CR_STATUS_MASK << CR_STATUS_SHIFT) 95 96 #define CR_CREDIT_RETURN_DUE_TO_PBC_SHIFT 12 97 #define CR_CREDIT_RETURN_DUE_TO_PBC_MASK 0x1ull 98 #define CR_CREDIT_RETURN_DUE_TO_PBC_SMASK \ 99 (CR_CREDIT_RETURN_DUE_TO_PBC_MASK << \ 100 CR_CREDIT_RETURN_DUE_TO_PBC_SHIFT) 101 102 #define CR_CREDIT_RETURN_DUE_TO_THRESHOLD_SHIFT 13 103 #define CR_CREDIT_RETURN_DUE_TO_THRESHOLD_MASK 0x1ull 104 #define CR_CREDIT_RETURN_DUE_TO_THRESHOLD_SMASK \ 105 (CR_CREDIT_RETURN_DUE_TO_THRESHOLD_MASK << \ 106 CR_CREDIT_RETURN_DUE_TO_THRESHOLD_SHIFT) 107 108 #define CR_CREDIT_RETURN_DUE_TO_ERR_SHIFT 14 109 #define CR_CREDIT_RETURN_DUE_TO_ERR_MASK 0x1ull 110 #define CR_CREDIT_RETURN_DUE_TO_ERR_SMASK \ 111 (CR_CREDIT_RETURN_DUE_TO_ERR_MASK << \ 112 CR_CREDIT_RETURN_DUE_TO_ERR_SHIFT) 113 114 #define CR_CREDIT_RETURN_DUE_TO_FORCE_SHIFT 15 115 #define CR_CREDIT_RETURN_DUE_TO_FORCE_MASK 0x1ull 116 #define CR_CREDIT_RETURN_DUE_TO_FORCE_SMASK \ 117 (CR_CREDIT_RETURN_DUE_TO_FORCE_MASK << \ 118 CR_CREDIT_RETURN_DUE_TO_FORCE_SHIFT) 119 120 /* Specific IRQ sources */ 121 #define CCE_ERR_INT 0 122 #define RXE_ERR_INT 1 123 #define MISC_ERR_INT 2 124 #define PIO_ERR_INT 4 125 #define SDMA_ERR_INT 5 126 #define EGRESS_ERR_INT 6 127 #define TXE_ERR_INT 7 128 #define PBC_INT 240 129 #define GPIO_ASSERT_INT 241 130 #define QSFP1_INT 242 131 #define QSFP2_INT 243 132 #define TCRIT_INT 244 133 134 /* interrupt source ranges */ 135 #define IS_FIRST_SOURCE CCE_ERR_INT 136 #define IS_GENERAL_ERR_START 0 137 #define IS_SDMAENG_ERR_START 16 138 #define IS_SENDCTXT_ERR_START 32 139 #define IS_SDMA_START 192 140 #define IS_SDMA_PROGRESS_START 208 141 #define IS_SDMA_IDLE_START 224 142 #define IS_VARIOUS_START 240 143 #define IS_DC_START 248 144 #define IS_RCVAVAIL_START 256 145 #define IS_RCVURGENT_START 416 146 #define IS_SENDCREDIT_START 576 147 #define IS_RESERVED_START 736 148 #define IS_LAST_SOURCE 767 149 150 /* derived interrupt source values */ 151 #define IS_GENERAL_ERR_END 7 152 #define IS_SDMAENG_ERR_END 31 153 #define IS_SENDCTXT_ERR_END 191 154 #define IS_SDMA_END 207 155 #define IS_SDMA_PROGRESS_END 223 156 #define IS_SDMA_IDLE_END 239 157 #define IS_VARIOUS_END 244 158 #define IS_DC_END 255 159 #define IS_RCVAVAIL_END 415 160 #define IS_RCVURGENT_END 575 161 #define IS_SENDCREDIT_END 735 162 #define IS_RESERVED_END IS_LAST_SOURCE 163 164 /* DCC_CFG_PORT_CONFIG logical link states */ 165 #define LSTATE_DOWN 0x1 166 #define LSTATE_INIT 0x2 167 #define LSTATE_ARMED 0x3 168 #define LSTATE_ACTIVE 0x4 169 170 /* DCC_CFG_RESET reset states */ 171 #define LCB_RX_FPE_TX_FPE_INTO_RESET (DCC_CFG_RESET_RESET_LCB | \ 172 DCC_CFG_RESET_RESET_TX_FPE | \ 173 DCC_CFG_RESET_RESET_RX_FPE | \ 174 DCC_CFG_RESET_ENABLE_CCLK_BCC) 175 /* 0x17 */ 176 177 #define LCB_RX_FPE_TX_FPE_OUT_OF_RESET DCC_CFG_RESET_ENABLE_CCLK_BCC /* 0x10 */ 178 179 /* DC8051_STS_CUR_STATE port values (physical link states) */ 180 #define PLS_DISABLED 0x30 181 #define PLS_OFFLINE 0x90 182 #define PLS_OFFLINE_QUIET 0x90 183 #define PLS_OFFLINE_PLANNED_DOWN_INFORM 0x91 184 #define PLS_OFFLINE_READY_TO_QUIET_LT 0x92 185 #define PLS_OFFLINE_REPORT_FAILURE 0x93 186 #define PLS_OFFLINE_READY_TO_QUIET_BCC 0x94 187 #define PLS_OFFLINE_QUIET_DURATION 0x95 188 #define PLS_POLLING 0x20 189 #define PLS_POLLING_QUIET 0x20 190 #define PLS_POLLING_ACTIVE 0x21 191 #define PLS_CONFIGPHY 0x40 192 #define PLS_CONFIGPHY_DEBOUCE 0x40 193 #define PLS_CONFIGPHY_ESTCOMM 0x41 194 #define PLS_CONFIGPHY_ESTCOMM_TXRX_HUNT 0x42 195 #define PLS_CONFIGPHY_ESTCOMM_LOCAL_COMPLETE 0x43 196 #define PLS_CONFIGPHY_OPTEQ 0x44 197 #define PLS_CONFIGPHY_OPTEQ_OPTIMIZING 0x44 198 #define PLS_CONFIGPHY_OPTEQ_LOCAL_COMPLETE 0x45 199 #define PLS_CONFIGPHY_VERIFYCAP 0x46 200 #define PLS_CONFIGPHY_VERIFYCAP_EXCHANGE 0x46 201 #define PLS_CONFIGPHY_VERIFYCAP_LOCAL_COMPLETE 0x47 202 #define PLS_CONFIGLT 0x48 203 #define PLS_CONFIGLT_CONFIGURE 0x48 204 #define PLS_CONFIGLT_LINK_TRANSFER_ACTIVE 0x49 205 #define PLS_LINKUP 0x50 206 #define PLS_PHYTEST 0xB0 207 #define PLS_INTERNAL_SERDES_LOOPBACK 0xe1 208 #define PLS_QUICK_LINKUP 0xe2 209 210 /* DC_DC8051_CFG_HOST_CMD_0.REQ_TYPE - 8051 host commands */ 211 #define HCMD_LOAD_CONFIG_DATA 0x01 212 #define HCMD_READ_CONFIG_DATA 0x02 213 #define HCMD_CHANGE_PHY_STATE 0x03 214 #define HCMD_SEND_LCB_IDLE_MSG 0x04 215 #define HCMD_MISC 0x05 216 #define HCMD_READ_LCB_IDLE_MSG 0x06 217 #define HCMD_READ_LCB_CSR 0x07 218 #define HCMD_WRITE_LCB_CSR 0x08 219 #define HCMD_INTERFACE_TEST 0xff 220 221 /* DC_DC8051_CFG_HOST_CMD_1.RETURN_CODE - 8051 host command return */ 222 #define HCMD_SUCCESS 2 223 224 /* DC_DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR - error flags */ 225 #define SPICO_ROM_FAILED BIT(0) 226 #define UNKNOWN_FRAME BIT(1) 227 #define TARGET_BER_NOT_MET BIT(2) 228 #define FAILED_SERDES_INTERNAL_LOOPBACK BIT(3) 229 #define FAILED_SERDES_INIT BIT(4) 230 #define FAILED_LNI_POLLING BIT(5) 231 #define FAILED_LNI_DEBOUNCE BIT(6) 232 #define FAILED_LNI_ESTBCOMM BIT(7) 233 #define FAILED_LNI_OPTEQ BIT(8) 234 #define FAILED_LNI_VERIFY_CAP1 BIT(9) 235 #define FAILED_LNI_VERIFY_CAP2 BIT(10) 236 #define FAILED_LNI_CONFIGLT BIT(11) 237 #define HOST_HANDSHAKE_TIMEOUT BIT(12) 238 #define EXTERNAL_DEVICE_REQ_TIMEOUT BIT(13) 239 240 #define FAILED_LNI (FAILED_LNI_POLLING | FAILED_LNI_DEBOUNCE \ 241 | FAILED_LNI_ESTBCOMM | FAILED_LNI_OPTEQ \ 242 | FAILED_LNI_VERIFY_CAP1 \ 243 | FAILED_LNI_VERIFY_CAP2 \ 244 | FAILED_LNI_CONFIGLT | HOST_HANDSHAKE_TIMEOUT \ 245 | EXTERNAL_DEVICE_REQ_TIMEOUT) 246 247 /* DC_DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG - host message flags */ 248 #define HOST_REQ_DONE BIT(0) 249 #define BC_PWR_MGM_MSG BIT(1) 250 #define BC_SMA_MSG BIT(2) 251 #define BC_BCC_UNKNOWN_MSG BIT(3) 252 #define BC_IDLE_UNKNOWN_MSG BIT(4) 253 #define EXT_DEVICE_CFG_REQ BIT(5) 254 #define VERIFY_CAP_FRAME BIT(6) 255 #define LINKUP_ACHIEVED BIT(7) 256 #define LINK_GOING_DOWN BIT(8) 257 #define LINK_WIDTH_DOWNGRADED BIT(9) 258 259 /* DC_DC8051_CFG_EXT_DEV_1.REQ_TYPE - 8051 host requests */ 260 #define HREQ_LOAD_CONFIG 0x01 261 #define HREQ_SAVE_CONFIG 0x02 262 #define HREQ_READ_CONFIG 0x03 263 #define HREQ_SET_TX_EQ_ABS 0x04 264 #define HREQ_SET_TX_EQ_REL 0x05 265 #define HREQ_ENABLE 0x06 266 #define HREQ_LCB_RESET 0x07 267 #define HREQ_CONFIG_DONE 0xfe 268 #define HREQ_INTERFACE_TEST 0xff 269 270 /* DC_DC8051_CFG_EXT_DEV_0.RETURN_CODE - 8051 host request return codes */ 271 #define HREQ_INVALID 0x01 272 #define HREQ_SUCCESS 0x02 273 #define HREQ_NOT_SUPPORTED 0x03 274 #define HREQ_FEATURE_NOT_SUPPORTED 0x04 /* request specific feature */ 275 #define HREQ_REQUEST_REJECTED 0xfe 276 #define HREQ_EXECUTION_ONGOING 0xff 277 278 /* MISC host command functions */ 279 #define HCMD_MISC_REQUEST_LCB_ACCESS 0x1 280 #define HCMD_MISC_GRANT_LCB_ACCESS 0x2 281 282 /* idle flit message types */ 283 #define IDLE_PHYSICAL_LINK_MGMT 0x1 284 #define IDLE_CRU 0x2 285 #define IDLE_SMA 0x3 286 #define IDLE_POWER_MGMT 0x4 287 288 /* idle flit message send fields (both send and read) */ 289 #define IDLE_PAYLOAD_MASK 0xffffffffffull /* 40 bits */ 290 #define IDLE_PAYLOAD_SHIFT 8 291 #define IDLE_MSG_TYPE_MASK 0xf 292 #define IDLE_MSG_TYPE_SHIFT 0 293 294 /* idle flit message read fields */ 295 #define READ_IDLE_MSG_TYPE_MASK 0xf 296 #define READ_IDLE_MSG_TYPE_SHIFT 0 297 298 /* SMA idle flit payload commands */ 299 #define SMA_IDLE_ARM 1 300 #define SMA_IDLE_ACTIVE 2 301 302 /* DC_DC8051_CFG_MODE.GENERAL bits */ 303 #define DISABLE_SELF_GUID_CHECK 0x2 304 305 /* Bad L2 frame error code */ 306 #define BAD_L2_ERR 0x6 307 308 /* 309 * Eager buffer minimum and maximum sizes supported by the hardware. 310 * All power-of-two sizes in between are supported as well. 311 * MAX_EAGER_BUFFER_TOTAL is the maximum size of memory 312 * allocatable for Eager buffer to a single context. All others 313 * are limits for the RcvArray entries. 314 */ 315 #define MIN_EAGER_BUFFER (4 * 1024) 316 #define MAX_EAGER_BUFFER (256 * 1024) 317 #define MAX_EAGER_BUFFER_TOTAL (64 * (1 << 20)) /* max per ctxt 64MB */ 318 #define MAX_EXPECTED_BUFFER (2048 * 1024) 319 #define HFI1_MIN_HDRQ_EGRBUF_CNT 32 320 #define HFI1_MAX_HDRQ_EGRBUF_CNT 16352 321 322 /* 323 * Receive expected base and count and eager base and count increment - 324 * the CSR fields hold multiples of this value. 325 */ 326 #define RCV_SHIFT 3 327 #define RCV_INCREMENT BIT(RCV_SHIFT) 328 329 /* 330 * Receive header queue entry increment - the CSR holds multiples of 331 * this value. 332 */ 333 #define HDRQ_SIZE_SHIFT 5 334 #define HDRQ_INCREMENT BIT(HDRQ_SIZE_SHIFT) 335 336 /* 337 * Freeze handling flags 338 */ 339 #define FREEZE_ABORT 0x01 /* do not do recovery */ 340 #define FREEZE_SELF 0x02 /* initiate the freeze */ 341 #define FREEZE_LINK_DOWN 0x04 /* link is down */ 342 343 /* 344 * Chip implementation codes. 345 */ 346 #define ICODE_RTL_SILICON 0x00 347 #define ICODE_RTL_VCS_SIMULATION 0x01 348 #define ICODE_FPGA_EMULATION 0x02 349 #define ICODE_FUNCTIONAL_SIMULATOR 0x03 350 351 /* 352 * 8051 data memory size. 353 */ 354 #define DC8051_DATA_MEM_SIZE 0x1000 355 356 /* 357 * 8051 firmware registers 358 */ 359 #define NUM_GENERAL_FIELDS 0x17 360 #define NUM_LANE_FIELDS 0x8 361 362 /* 8051 general register Field IDs */ 363 #define LINK_OPTIMIZATION_SETTINGS 0x00 364 #define LINK_TUNING_PARAMETERS 0x02 365 #define DC_HOST_COMM_SETTINGS 0x03 366 #define TX_SETTINGS 0x06 367 #define VERIFY_CAP_LOCAL_PHY 0x07 368 #define VERIFY_CAP_LOCAL_FABRIC 0x08 369 #define VERIFY_CAP_LOCAL_LINK_MODE 0x09 370 #define LOCAL_DEVICE_ID 0x0a 371 #define RESERVED_REGISTERS 0x0b 372 #define LOCAL_LNI_INFO 0x0c 373 #define REMOTE_LNI_INFO 0x0d 374 #define MISC_STATUS 0x0e 375 #define VERIFY_CAP_REMOTE_PHY 0x0f 376 #define VERIFY_CAP_REMOTE_FABRIC 0x10 377 #define VERIFY_CAP_REMOTE_LINK_WIDTH 0x11 378 #define LAST_LOCAL_STATE_COMPLETE 0x12 379 #define LAST_REMOTE_STATE_COMPLETE 0x13 380 #define LINK_QUALITY_INFO 0x14 381 #define REMOTE_DEVICE_ID 0x15 382 #define LINK_DOWN_REASON 0x16 /* first byte of offset 0x16 */ 383 #define VERSION_PATCH 0x16 /* last byte of offset 0x16 */ 384 385 /* 8051 lane specific register field IDs */ 386 #define TX_EQ_SETTINGS 0x00 387 #define CHANNEL_LOSS_SETTINGS 0x05 388 389 /* Lane ID for general configuration registers */ 390 #define GENERAL_CONFIG 4 391 392 /* LINK_TUNING_PARAMETERS fields */ 393 #define TUNING_METHOD_SHIFT 24 394 395 /* LINK_OPTIMIZATION_SETTINGS fields */ 396 #define ENABLE_EXT_DEV_CONFIG_SHIFT 24 397 398 /* LOAD_DATA 8051 command shifts and fields */ 399 #define LOAD_DATA_FIELD_ID_SHIFT 40 400 #define LOAD_DATA_FIELD_ID_MASK 0xfull 401 #define LOAD_DATA_LANE_ID_SHIFT 32 402 #define LOAD_DATA_LANE_ID_MASK 0xfull 403 #define LOAD_DATA_DATA_SHIFT 0x0 404 #define LOAD_DATA_DATA_MASK 0xffffffffull 405 406 /* READ_DATA 8051 command shifts and fields */ 407 #define READ_DATA_FIELD_ID_SHIFT 40 408 #define READ_DATA_FIELD_ID_MASK 0xffull 409 #define READ_DATA_LANE_ID_SHIFT 32 410 #define READ_DATA_LANE_ID_MASK 0xffull 411 #define READ_DATA_DATA_SHIFT 0x0 412 #define READ_DATA_DATA_MASK 0xffffffffull 413 414 /* TX settings fields */ 415 #define ENABLE_LANE_TX_SHIFT 0 416 #define ENABLE_LANE_TX_MASK 0xff 417 #define TX_POLARITY_INVERSION_SHIFT 8 418 #define TX_POLARITY_INVERSION_MASK 0xff 419 #define RX_POLARITY_INVERSION_SHIFT 16 420 #define RX_POLARITY_INVERSION_MASK 0xff 421 #define MAX_RATE_SHIFT 24 422 #define MAX_RATE_MASK 0xff 423 424 /* verify capability PHY fields */ 425 #define CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT 0x4 426 #define CONTINIOUS_REMOTE_UPDATE_SUPPORT_MASK 0x1 427 #define POWER_MANAGEMENT_SHIFT 0x0 428 #define POWER_MANAGEMENT_MASK 0xf 429 430 /* 8051 lane register Field IDs */ 431 #define SPICO_FW_VERSION 0x7 /* SPICO firmware version */ 432 433 /* SPICO firmware version fields */ 434 #define SPICO_ROM_VERSION_SHIFT 0 435 #define SPICO_ROM_VERSION_MASK 0xffff 436 #define SPICO_ROM_PROD_ID_SHIFT 16 437 #define SPICO_ROM_PROD_ID_MASK 0xffff 438 439 /* verify capability fabric fields */ 440 #define VAU_SHIFT 0 441 #define VAU_MASK 0x0007 442 #define Z_SHIFT 3 443 #define Z_MASK 0x0001 444 #define VCU_SHIFT 4 445 #define VCU_MASK 0x0007 446 #define VL15BUF_SHIFT 8 447 #define VL15BUF_MASK 0x0fff 448 #define CRC_SIZES_SHIFT 20 449 #define CRC_SIZES_MASK 0x7 450 451 /* verify capability local link width fields */ 452 #define LINK_WIDTH_SHIFT 0 /* also for remote link width */ 453 #define LINK_WIDTH_MASK 0xffff /* also for remote link width */ 454 #define LOCAL_FLAG_BITS_SHIFT 16 455 #define LOCAL_FLAG_BITS_MASK 0xff 456 #define MISC_CONFIG_BITS_SHIFT 24 457 #define MISC_CONFIG_BITS_MASK 0xff 458 459 /* verify capability remote link width fields */ 460 #define REMOTE_TX_RATE_SHIFT 16 461 #define REMOTE_TX_RATE_MASK 0xff 462 463 /* LOCAL_DEVICE_ID fields */ 464 #define LOCAL_DEVICE_REV_SHIFT 0 465 #define LOCAL_DEVICE_REV_MASK 0xff 466 #define LOCAL_DEVICE_ID_SHIFT 8 467 #define LOCAL_DEVICE_ID_MASK 0xffff 468 469 /* REMOTE_DEVICE_ID fields */ 470 #define REMOTE_DEVICE_REV_SHIFT 0 471 #define REMOTE_DEVICE_REV_MASK 0xff 472 #define REMOTE_DEVICE_ID_SHIFT 8 473 #define REMOTE_DEVICE_ID_MASK 0xffff 474 475 /* local LNI link width fields */ 476 #define ENABLE_LANE_RX_SHIFT 16 477 #define ENABLE_LANE_RX_MASK 0xff 478 479 /* mask, shift for reading 'mgmt_enabled' value from REMOTE_LNI_INFO field */ 480 #define MGMT_ALLOWED_SHIFT 23 481 #define MGMT_ALLOWED_MASK 0x1 482 483 /* mask, shift for 'link_quality' within LINK_QUALITY_INFO field */ 484 #define LINK_QUALITY_SHIFT 24 485 #define LINK_QUALITY_MASK 0x7 486 487 /* 488 * mask, shift for reading 'planned_down_remote_reason_code' 489 * from LINK_QUALITY_INFO field 490 */ 491 #define DOWN_REMOTE_REASON_SHIFT 16 492 #define DOWN_REMOTE_REASON_MASK 0xff 493 494 #define HOST_INTERFACE_VERSION 1 495 #define HOST_INTERFACE_VERSION_SHIFT 16 496 #define HOST_INTERFACE_VERSION_MASK 0xff 497 498 /* verify capability PHY power management bits */ 499 #define PWRM_BER_CONTROL 0x1 500 #define PWRM_BANDWIDTH_CONTROL 0x2 501 502 /* 8051 link down reasons */ 503 #define LDR_LINK_TRANSFER_ACTIVE_LOW 0xa 504 #define LDR_RECEIVED_LINKDOWN_IDLE_MSG 0xb 505 #define LDR_RECEIVED_HOST_OFFLINE_REQ 0xc 506 507 /* verify capability fabric CRC size bits */ 508 enum { 509 CAP_CRC_14B = (1 << 0), /* 14b CRC */ 510 CAP_CRC_48B = (1 << 1), /* 48b CRC */ 511 CAP_CRC_12B_16B_PER_LANE = (1 << 2) /* 12b-16b per lane CRC */ 512 }; 513 514 #define SUPPORTED_CRCS (CAP_CRC_14B | CAP_CRC_48B) 515 516 /* misc status version fields */ 517 #define STS_FM_VERSION_MINOR_SHIFT 16 518 #define STS_FM_VERSION_MINOR_MASK 0xff 519 #define STS_FM_VERSION_MAJOR_SHIFT 24 520 #define STS_FM_VERSION_MAJOR_MASK 0xff 521 #define STS_FM_VERSION_PATCH_SHIFT 24 522 #define STS_FM_VERSION_PATCH_MASK 0xff 523 524 /* LCB_CFG_CRC_MODE TX_VAL and RX_VAL CRC mode values */ 525 #define LCB_CRC_16B 0x0 /* 16b CRC */ 526 #define LCB_CRC_14B 0x1 /* 14b CRC */ 527 #define LCB_CRC_48B 0x2 /* 48b CRC */ 528 #define LCB_CRC_12B_16B_PER_LANE 0x3 /* 12b-16b per lane CRC */ 529 530 /* 531 * the following enum is (almost) a copy/paste of the definition 532 * in the OPA spec, section 20.2.2.6.8 (PortInfo) 533 */ 534 enum { 535 PORT_LTP_CRC_MODE_NONE = 0, 536 PORT_LTP_CRC_MODE_14 = 1, /* 14-bit LTP CRC mode (optional) */ 537 PORT_LTP_CRC_MODE_16 = 2, /* 16-bit LTP CRC mode */ 538 PORT_LTP_CRC_MODE_48 = 4, 539 /* 48-bit overlapping LTP CRC mode (optional) */ 540 PORT_LTP_CRC_MODE_PER_LANE = 8 541 /* 12 to 16 bit per lane LTP CRC mode (optional) */ 542 }; 543 544 /* timeouts */ 545 #define LINK_RESTART_DELAY 1000 /* link restart delay, in ms */ 546 #define TIMEOUT_8051_START 5000 /* 8051 start timeout, in ms */ 547 #define DC8051_COMMAND_TIMEOUT 1000 /* DC8051 command timeout, in ms */ 548 #define FREEZE_STATUS_TIMEOUT 20 /* wait for freeze indicators, in ms */ 549 #define VL_STATUS_CLEAR_TIMEOUT 5000 /* per-VL status clear, in ms */ 550 #define CCE_STATUS_TIMEOUT 10 /* time to clear CCE Status, in ms */ 551 552 /* cclock tick time, in picoseconds per tick: 1/speed * 10^12 */ 553 #define ASIC_CCLOCK_PS 1242 /* 805 MHz */ 554 #define FPGA_CCLOCK_PS 30300 /* 33 MHz */ 555 556 /* 557 * Mask of enabled MISC errors. Do not enable the two RSA engine errors - 558 * see firmware.c:run_rsa() for details. 559 */ 560 #define DRIVER_MISC_MASK \ 561 (~(MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK \ 562 | MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK)) 563 564 /* valid values for the loopback module parameter */ 565 #define LOOPBACK_NONE 0 /* no loopback - default */ 566 #define LOOPBACK_SERDES 1 567 #define LOOPBACK_LCB 2 568 #define LOOPBACK_CABLE 3 /* external cable */ 569 570 /* set up bits in MISC_CONFIG_BITS */ 571 #define LOOPBACK_SERDES_CONFIG_BIT_MASK_SHIFT 0 572 #define EXT_CFG_LCB_RESET_SUPPORTED_SHIFT 3 573 574 /* read and write hardware registers */ 575 u64 read_csr(const struct hfi1_devdata *dd, u32 offset); 576 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value); 577 578 /* 579 * The *_kctxt_* flavor of the CSR read/write functions are for 580 * per-context or per-SDMA CSRs that are not mappable to user-space. 581 * Their spacing is not a PAGE_SIZE multiple. 582 */ read_kctxt_csr(const struct hfi1_devdata * dd,int ctxt,u32 offset0)583 static inline u64 read_kctxt_csr(const struct hfi1_devdata *dd, int ctxt, 584 u32 offset0) 585 { 586 /* kernel per-context CSRs are separated by 0x100 */ 587 return read_csr(dd, offset0 + (0x100 * ctxt)); 588 } 589 write_kctxt_csr(struct hfi1_devdata * dd,int ctxt,u32 offset0,u64 value)590 static inline void write_kctxt_csr(struct hfi1_devdata *dd, int ctxt, 591 u32 offset0, u64 value) 592 { 593 /* kernel per-context CSRs are separated by 0x100 */ 594 write_csr(dd, offset0 + (0x100 * ctxt), value); 595 } 596 597 int read_lcb_csr(struct hfi1_devdata *dd, u32 offset, u64 *data); 598 int write_lcb_csr(struct hfi1_devdata *dd, u32 offset, u64 data); 599 600 void __iomem *get_csr_addr( 601 const struct hfi1_devdata *dd, 602 u32 offset); 603 get_kctxt_csr_addr(const struct hfi1_devdata * dd,int ctxt,u32 offset0)604 static inline void __iomem *get_kctxt_csr_addr( 605 const struct hfi1_devdata *dd, 606 int ctxt, 607 u32 offset0) 608 { 609 return get_csr_addr(dd, offset0 + (0x100 * ctxt)); 610 } 611 612 /* 613 * The *_uctxt_* flavor of the CSR read/write functions are for 614 * per-context CSRs that are mappable to user space. All these CSRs 615 * are spaced by a PAGE_SIZE multiple in order to be mappable to 616 * different processes without exposing other contexts' CSRs 617 */ read_uctxt_csr(const struct hfi1_devdata * dd,int ctxt,u32 offset0)618 static inline u64 read_uctxt_csr(const struct hfi1_devdata *dd, int ctxt, 619 u32 offset0) 620 { 621 /* user per-context CSRs are separated by 0x1000 */ 622 return read_csr(dd, offset0 + (0x1000 * ctxt)); 623 } 624 write_uctxt_csr(struct hfi1_devdata * dd,int ctxt,u32 offset0,u64 value)625 static inline void write_uctxt_csr(struct hfi1_devdata *dd, int ctxt, 626 u32 offset0, u64 value) 627 { 628 /* user per-context CSRs are separated by 0x1000 */ 629 write_csr(dd, offset0 + (0x1000 * ctxt), value); 630 } 631 chip_rcv_contexts(struct hfi1_devdata * dd)632 static inline u32 chip_rcv_contexts(struct hfi1_devdata *dd) 633 { 634 return read_csr(dd, RCV_CONTEXTS); 635 } 636 chip_send_contexts(struct hfi1_devdata * dd)637 static inline u32 chip_send_contexts(struct hfi1_devdata *dd) 638 { 639 return read_csr(dd, SEND_CONTEXTS); 640 } 641 chip_sdma_engines(struct hfi1_devdata * dd)642 static inline u32 chip_sdma_engines(struct hfi1_devdata *dd) 643 { 644 return read_csr(dd, SEND_DMA_ENGINES); 645 } 646 chip_pio_mem_size(struct hfi1_devdata * dd)647 static inline u32 chip_pio_mem_size(struct hfi1_devdata *dd) 648 { 649 return read_csr(dd, SEND_PIO_MEM_SIZE); 650 } 651 chip_sdma_mem_size(struct hfi1_devdata * dd)652 static inline u32 chip_sdma_mem_size(struct hfi1_devdata *dd) 653 { 654 return read_csr(dd, SEND_DMA_MEM_SIZE); 655 } 656 chip_rcv_array_count(struct hfi1_devdata * dd)657 static inline u32 chip_rcv_array_count(struct hfi1_devdata *dd) 658 { 659 return read_csr(dd, RCV_ARRAY_CNT); 660 } 661 662 u8 encode_rcv_header_entry_size(u8 size); 663 int hfi1_validate_rcvhdrcnt(struct hfi1_devdata *dd, uint thecnt); 664 void set_hdrq_regs(struct hfi1_devdata *dd, u8 ctxt, u8 entsize, u16 hdrcnt); 665 666 u64 create_pbc(struct hfi1_pportdata *ppd, u64 flags, int srate_mbs, u32 vl, 667 u32 dw_len); 668 669 /* firmware.c */ 670 #define SBUS_MASTER_BROADCAST 0xfd 671 #define NUM_PCIE_SERDES 16 /* number of PCIe serdes on the SBus */ 672 extern const u8 pcie_serdes_broadcast[]; 673 extern const u8 pcie_pcs_addrs[2][NUM_PCIE_SERDES]; 674 675 /* SBus commands */ 676 #define RESET_SBUS_RECEIVER 0x20 677 #define WRITE_SBUS_RECEIVER 0x21 678 #define READ_SBUS_RECEIVER 0x22 679 void sbus_request(struct hfi1_devdata *dd, 680 u8 receiver_addr, u8 data_addr, u8 command, u32 data_in); 681 int sbus_request_slow(struct hfi1_devdata *dd, 682 u8 receiver_addr, u8 data_addr, u8 command, u32 data_in); 683 void set_sbus_fast_mode(struct hfi1_devdata *dd); 684 void clear_sbus_fast_mode(struct hfi1_devdata *dd); 685 int hfi1_firmware_init(struct hfi1_devdata *dd); 686 int load_pcie_firmware(struct hfi1_devdata *dd); 687 int load_firmware(struct hfi1_devdata *dd); 688 void dispose_firmware(void); 689 int acquire_hw_mutex(struct hfi1_devdata *dd); 690 void release_hw_mutex(struct hfi1_devdata *dd); 691 692 /* 693 * Bitmask of dynamic access for ASIC block chip resources. Each HFI has its 694 * own range of bits for the resource so it can clear its own bits on 695 * starting and exiting. If either HFI has the resource bit set, the 696 * resource is in use. The separate bit ranges are: 697 * HFI0 bits 7:0 698 * HFI1 bits 15:8 699 */ 700 #define CR_SBUS 0x01 /* SBUS, THERM, and PCIE registers */ 701 #define CR_EPROM 0x02 /* EEP, GPIO registers */ 702 #define CR_I2C1 0x04 /* QSFP1_OE register */ 703 #define CR_I2C2 0x08 /* QSFP2_OE register */ 704 #define CR_DYN_SHIFT 8 /* dynamic flag shift */ 705 #define CR_DYN_MASK ((1ull << CR_DYN_SHIFT) - 1) 706 707 /* 708 * Bitmask of static ASIC states these are outside of the dynamic ASIC 709 * block chip resources above. These are to be set once and never cleared. 710 * Must be holding the SBus dynamic flag when setting. 711 */ 712 #define CR_THERM_INIT 0x010000 713 714 int acquire_chip_resource(struct hfi1_devdata *dd, u32 resource, u32 mswait); 715 void release_chip_resource(struct hfi1_devdata *dd, u32 resource); 716 bool check_chip_resource(struct hfi1_devdata *dd, u32 resource, 717 const char *func); 718 void init_chip_resources(struct hfi1_devdata *dd); 719 void finish_chip_resources(struct hfi1_devdata *dd); 720 721 /* ms wait time for access to an SBus resoure */ 722 #define SBUS_TIMEOUT 4000 /* long enough for a FW download and SBR */ 723 724 /* ms wait time for a qsfp (i2c) chain to become available */ 725 #define QSFP_WAIT 20000 /* long enough for FW update to the F4 uc */ 726 727 void fabric_serdes_reset(struct hfi1_devdata *dd); 728 int read_8051_data(struct hfi1_devdata *dd, u32 addr, u32 len, u64 *result); 729 730 /* chip.c */ 731 void read_misc_status(struct hfi1_devdata *dd, u8 *ver_major, u8 *ver_minor, 732 u8 *ver_patch); 733 int write_host_interface_version(struct hfi1_devdata *dd, u8 version); 734 void read_guid(struct hfi1_devdata *dd); 735 int wait_fm_ready(struct hfi1_devdata *dd, u32 mstimeout); 736 void set_link_down_reason(struct hfi1_pportdata *ppd, u8 lcl_reason, 737 u8 neigh_reason, u8 rem_reason); 738 int set_link_state(struct hfi1_pportdata *, u32 state); 739 int port_ltp_to_cap(int port_ltp); 740 void handle_verify_cap(struct work_struct *work); 741 void handle_freeze(struct work_struct *work); 742 void handle_link_up(struct work_struct *work); 743 void handle_link_down(struct work_struct *work); 744 void handle_link_downgrade(struct work_struct *work); 745 void handle_link_bounce(struct work_struct *work); 746 void handle_start_link(struct work_struct *work); 747 void handle_sma_message(struct work_struct *work); 748 int reset_qsfp(struct hfi1_pportdata *ppd); 749 void qsfp_event(struct work_struct *work); 750 void start_freeze_handling(struct hfi1_pportdata *ppd, int flags); 751 int send_idle_sma(struct hfi1_devdata *dd, u64 message); 752 int load_8051_config(struct hfi1_devdata *, u8, u8, u32); 753 int read_8051_config(struct hfi1_devdata *, u8, u8, u32 *); 754 int start_link(struct hfi1_pportdata *ppd); 755 int bringup_serdes(struct hfi1_pportdata *ppd); 756 void set_intr_state(struct hfi1_devdata *dd, u32 enable); 757 bool apply_link_downgrade_policy(struct hfi1_pportdata *ppd, 758 bool refresh_widths); 759 void update_usrhead(struct hfi1_ctxtdata *rcd, u32 hd, u32 updegr, u32 egrhd, 760 u32 intr_adjust, u32 npkts); 761 int stop_drain_data_vls(struct hfi1_devdata *dd); 762 int open_fill_data_vls(struct hfi1_devdata *dd); 763 u32 ns_to_cclock(struct hfi1_devdata *dd, u32 ns); 764 u32 cclock_to_ns(struct hfi1_devdata *dd, u32 cclock); 765 void get_linkup_link_widths(struct hfi1_pportdata *ppd); 766 void read_ltp_rtt(struct hfi1_devdata *dd); 767 void clear_linkup_counters(struct hfi1_devdata *dd); 768 u32 hdrqempty(struct hfi1_ctxtdata *rcd); 769 int is_ax(struct hfi1_devdata *dd); 770 int is_bx(struct hfi1_devdata *dd); 771 bool is_urg_masked(struct hfi1_ctxtdata *rcd); 772 u32 read_physical_state(struct hfi1_devdata *dd); 773 u32 chip_to_opa_pstate(struct hfi1_devdata *dd, u32 chip_pstate); 774 const char *opa_lstate_name(u32 lstate); 775 const char *opa_pstate_name(u32 pstate); 776 u32 driver_pstate(struct hfi1_pportdata *ppd); 777 u32 driver_lstate(struct hfi1_pportdata *ppd); 778 779 int acquire_lcb_access(struct hfi1_devdata *dd, int sleep_ok); 780 int release_lcb_access(struct hfi1_devdata *dd, int sleep_ok); 781 #define LCB_START DC_LCB_CSRS 782 #define LCB_END DC_8051_CSRS /* next block is 8051 */ 783 extern uint num_vls; 784 785 extern uint disable_integrity; 786 u64 read_dev_cntr(struct hfi1_devdata *dd, int index, int vl); 787 u64 write_dev_cntr(struct hfi1_devdata *dd, int index, int vl, u64 data); 788 u64 read_port_cntr(struct hfi1_pportdata *ppd, int index, int vl); 789 u64 write_port_cntr(struct hfi1_pportdata *ppd, int index, int vl, u64 data); 790 u32 read_logical_state(struct hfi1_devdata *dd); 791 void force_recv_intr(struct hfi1_ctxtdata *rcd); 792 793 /* Per VL indexes */ 794 enum { 795 C_VL_0 = 0, 796 C_VL_1, 797 C_VL_2, 798 C_VL_3, 799 C_VL_4, 800 C_VL_5, 801 C_VL_6, 802 C_VL_7, 803 C_VL_15, 804 C_VL_COUNT 805 }; 806 vl_from_idx(int idx)807 static inline int vl_from_idx(int idx) 808 { 809 return (idx == C_VL_15 ? 15 : idx); 810 } 811 idx_from_vl(int vl)812 static inline int idx_from_vl(int vl) 813 { 814 return (vl == 15 ? C_VL_15 : vl); 815 } 816 817 /* Per device counter indexes */ 818 enum { 819 C_RCV_OVF = 0, 820 C_RX_LEN_ERR, 821 C_RX_SHORT_ERR, 822 C_RX_ICRC_ERR, 823 C_RX_EBP, 824 C_RX_TID_FULL, 825 C_RX_TID_INVALID, 826 C_RX_TID_FLGMS, 827 C_RX_CTX_EGRS, 828 C_RCV_TID_FLSMS, 829 C_CCE_PCI_CR_ST, 830 C_CCE_PCI_TR_ST, 831 C_CCE_PIO_WR_ST, 832 C_CCE_ERR_INT, 833 C_CCE_SDMA_INT, 834 C_CCE_MISC_INT, 835 C_CCE_RCV_AV_INT, 836 C_CCE_RCV_URG_INT, 837 C_CCE_SEND_CR_INT, 838 C_DC_UNC_ERR, 839 C_DC_RCV_ERR, 840 C_DC_FM_CFG_ERR, 841 C_DC_RMT_PHY_ERR, 842 C_DC_DROPPED_PKT, 843 C_DC_MC_XMIT_PKTS, 844 C_DC_MC_RCV_PKTS, 845 C_DC_XMIT_CERR, 846 C_DC_RCV_CERR, 847 C_DC_RCV_FCC, 848 C_DC_XMIT_FCC, 849 C_DC_XMIT_FLITS, 850 C_DC_RCV_FLITS, 851 C_DC_XMIT_PKTS, 852 C_DC_RCV_PKTS, 853 C_DC_RX_FLIT_VL, 854 C_DC_RX_PKT_VL, 855 C_DC_RCV_FCN, 856 C_DC_RCV_FCN_VL, 857 C_DC_RCV_BCN, 858 C_DC_RCV_BCN_VL, 859 C_DC_RCV_BBL, 860 C_DC_RCV_BBL_VL, 861 C_DC_MARK_FECN, 862 C_DC_MARK_FECN_VL, 863 C_DC_TOTAL_CRC, 864 C_DC_CRC_LN0, 865 C_DC_CRC_LN1, 866 C_DC_CRC_LN2, 867 C_DC_CRC_LN3, 868 C_DC_CRC_MULT_LN, 869 C_DC_TX_REPLAY, 870 C_DC_RX_REPLAY, 871 C_DC_SEQ_CRC_CNT, 872 C_DC_ESC0_ONLY_CNT, 873 C_DC_ESC0_PLUS1_CNT, 874 C_DC_ESC0_PLUS2_CNT, 875 C_DC_REINIT_FROM_PEER_CNT, 876 C_DC_SBE_CNT, 877 C_DC_MISC_FLG_CNT, 878 C_DC_PRF_GOOD_LTP_CNT, 879 C_DC_PRF_ACCEPTED_LTP_CNT, 880 C_DC_PRF_RX_FLIT_CNT, 881 C_DC_PRF_TX_FLIT_CNT, 882 C_DC_PRF_CLK_CNTR, 883 C_DC_PG_DBG_FLIT_CRDTS_CNT, 884 C_DC_PG_STS_PAUSE_COMPLETE_CNT, 885 C_DC_PG_STS_TX_SBE_CNT, 886 C_DC_PG_STS_TX_MBE_CNT, 887 C_SW_CPU_INTR, 888 C_SW_CPU_RCV_LIM, 889 C_SW_CTX0_SEQ_DROP, 890 C_SW_VTX_WAIT, 891 C_SW_PIO_WAIT, 892 C_SW_PIO_DRAIN, 893 C_SW_KMEM_WAIT, 894 C_SW_TID_WAIT, 895 C_SW_SEND_SCHED, 896 C_SDMA_DESC_FETCHED_CNT, 897 C_SDMA_INT_CNT, 898 C_SDMA_ERR_CNT, 899 C_SDMA_IDLE_INT_CNT, 900 C_SDMA_PROGRESS_INT_CNT, 901 /* MISC_ERR_STATUS */ 902 C_MISC_PLL_LOCK_FAIL_ERR, 903 C_MISC_MBIST_FAIL_ERR, 904 C_MISC_INVALID_EEP_CMD_ERR, 905 C_MISC_EFUSE_DONE_PARITY_ERR, 906 C_MISC_EFUSE_WRITE_ERR, 907 C_MISC_EFUSE_READ_BAD_ADDR_ERR, 908 C_MISC_EFUSE_CSR_PARITY_ERR, 909 C_MISC_FW_AUTH_FAILED_ERR, 910 C_MISC_KEY_MISMATCH_ERR, 911 C_MISC_SBUS_WRITE_FAILED_ERR, 912 C_MISC_CSR_WRITE_BAD_ADDR_ERR, 913 C_MISC_CSR_READ_BAD_ADDR_ERR, 914 C_MISC_CSR_PARITY_ERR, 915 /* CceErrStatus */ 916 /* 917 * A special counter that is the aggregate count 918 * of all the cce_err_status errors. The remainder 919 * are actual bits in the CceErrStatus register. 920 */ 921 C_CCE_ERR_STATUS_AGGREGATED_CNT, 922 C_CCE_MSIX_CSR_PARITY_ERR, 923 C_CCE_INT_MAP_UNC_ERR, 924 C_CCE_INT_MAP_COR_ERR, 925 C_CCE_MSIX_TABLE_UNC_ERR, 926 C_CCE_MSIX_TABLE_COR_ERR, 927 C_CCE_RXDMA_CONV_FIFO_PARITY_ERR, 928 C_CCE_RCPL_ASYNC_FIFO_PARITY_ERR, 929 C_CCE_SEG_WRITE_BAD_ADDR_ERR, 930 C_CCE_SEG_READ_BAD_ADDR_ERR, 931 C_LA_TRIGGERED, 932 C_CCE_TRGT_CPL_TIMEOUT_ERR, 933 C_PCIC_RECEIVE_PARITY_ERR, 934 C_PCIC_TRANSMIT_BACK_PARITY_ERR, 935 C_PCIC_TRANSMIT_FRONT_PARITY_ERR, 936 C_PCIC_CPL_DAT_Q_UNC_ERR, 937 C_PCIC_CPL_HD_Q_UNC_ERR, 938 C_PCIC_POST_DAT_Q_UNC_ERR, 939 C_PCIC_POST_HD_Q_UNC_ERR, 940 C_PCIC_RETRY_SOT_MEM_UNC_ERR, 941 C_PCIC_RETRY_MEM_UNC_ERR, 942 C_PCIC_N_POST_DAT_Q_PARITY_ERR, 943 C_PCIC_N_POST_H_Q_PARITY_ERR, 944 C_PCIC_CPL_DAT_Q_COR_ERR, 945 C_PCIC_CPL_HD_Q_COR_ERR, 946 C_PCIC_POST_DAT_Q_COR_ERR, 947 C_PCIC_POST_HD_Q_COR_ERR, 948 C_PCIC_RETRY_SOT_MEM_COR_ERR, 949 C_PCIC_RETRY_MEM_COR_ERR, 950 C_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERR, 951 C_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERR, 952 C_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR, 953 C_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR, 954 C_CCE_CLI2_ASYNC_FIFO_PARITY_ERR, 955 C_CCE_CSR_CFG_BUS_PARITY_ERR, 956 C_CCE_CLI0_ASYNC_FIFO_PARTIY_ERR, 957 C_CCE_RSPD_DATA_PARITY_ERR, 958 C_CCE_TRGT_ACCESS_ERR, 959 C_CCE_TRGT_ASYNC_FIFO_PARITY_ERR, 960 C_CCE_CSR_WRITE_BAD_ADDR_ERR, 961 C_CCE_CSR_READ_BAD_ADDR_ERR, 962 C_CCE_CSR_PARITY_ERR, 963 /* RcvErrStatus */ 964 C_RX_CSR_PARITY_ERR, 965 C_RX_CSR_WRITE_BAD_ADDR_ERR, 966 C_RX_CSR_READ_BAD_ADDR_ERR, 967 C_RX_DMA_CSR_UNC_ERR, 968 C_RX_DMA_DQ_FSM_ENCODING_ERR, 969 C_RX_DMA_EQ_FSM_ENCODING_ERR, 970 C_RX_DMA_CSR_PARITY_ERR, 971 C_RX_RBUF_DATA_COR_ERR, 972 C_RX_RBUF_DATA_UNC_ERR, 973 C_RX_DMA_DATA_FIFO_RD_COR_ERR, 974 C_RX_DMA_DATA_FIFO_RD_UNC_ERR, 975 C_RX_DMA_HDR_FIFO_RD_COR_ERR, 976 C_RX_DMA_HDR_FIFO_RD_UNC_ERR, 977 C_RX_RBUF_DESC_PART2_COR_ERR, 978 C_RX_RBUF_DESC_PART2_UNC_ERR, 979 C_RX_RBUF_DESC_PART1_COR_ERR, 980 C_RX_RBUF_DESC_PART1_UNC_ERR, 981 C_RX_HQ_INTR_FSM_ERR, 982 C_RX_HQ_INTR_CSR_PARITY_ERR, 983 C_RX_LOOKUP_CSR_PARITY_ERR, 984 C_RX_LOOKUP_RCV_ARRAY_COR_ERR, 985 C_RX_LOOKUP_RCV_ARRAY_UNC_ERR, 986 C_RX_LOOKUP_DES_PART2_PARITY_ERR, 987 C_RX_LOOKUP_DES_PART1_UNC_COR_ERR, 988 C_RX_LOOKUP_DES_PART1_UNC_ERR, 989 C_RX_RBUF_NEXT_FREE_BUF_COR_ERR, 990 C_RX_RBUF_NEXT_FREE_BUF_UNC_ERR, 991 C_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR, 992 C_RX_RBUF_FL_INITDONE_PARITY_ERR, 993 C_RX_RBUF_FL_WRITE_ADDR_PARITY_ERR, 994 C_RX_RBUF_FL_RD_ADDR_PARITY_ERR, 995 C_RX_RBUF_EMPTY_ERR, 996 C_RX_RBUF_FULL_ERR, 997 C_RX_RBUF_BAD_LOOKUP_ERR, 998 C_RX_RBUF_CTX_ID_PARITY_ERR, 999 C_RX_RBUF_CSR_QEOPDW_PARITY_ERR, 1000 C_RX_RBUF_CSR_Q_NUM_OF_PKT_PARITY_ERR, 1001 C_RX_RBUF_CSR_Q_T1_PTR_PARITY_ERR, 1002 C_RX_RBUF_CSR_Q_HD_PTR_PARITY_ERR, 1003 C_RX_RBUF_CSR_Q_VLD_BIT_PARITY_ERR, 1004 C_RX_RBUF_CSR_Q_NEXT_BUF_PARITY_ERR, 1005 C_RX_RBUF_CSR_Q_ENT_CNT_PARITY_ERR, 1006 C_RX_RBUF_CSR_Q_HEAD_BUF_NUM_PARITY_ERR, 1007 C_RX_RBUF_BLOCK_LIST_READ_COR_ERR, 1008 C_RX_RBUF_BLOCK_LIST_READ_UNC_ERR, 1009 C_RX_RBUF_LOOKUP_DES_COR_ERR, 1010 C_RX_RBUF_LOOKUP_DES_UNC_ERR, 1011 C_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR, 1012 C_RX_RBUF_LOOKUP_DES_REG_UNC_ERR, 1013 C_RX_RBUF_FREE_LIST_COR_ERR, 1014 C_RX_RBUF_FREE_LIST_UNC_ERR, 1015 C_RX_RCV_FSM_ENCODING_ERR, 1016 C_RX_DMA_FLAG_COR_ERR, 1017 C_RX_DMA_FLAG_UNC_ERR, 1018 C_RX_DC_SOP_EOP_PARITY_ERR, 1019 C_RX_RCV_CSR_PARITY_ERR, 1020 C_RX_RCV_QP_MAP_TABLE_COR_ERR, 1021 C_RX_RCV_QP_MAP_TABLE_UNC_ERR, 1022 C_RX_RCV_DATA_COR_ERR, 1023 C_RX_RCV_DATA_UNC_ERR, 1024 C_RX_RCV_HDR_COR_ERR, 1025 C_RX_RCV_HDR_UNC_ERR, 1026 C_RX_DC_INTF_PARITY_ERR, 1027 C_RX_DMA_CSR_COR_ERR, 1028 /* SendPioErrStatus */ 1029 C_PIO_PEC_SOP_HEAD_PARITY_ERR, 1030 C_PIO_PCC_SOP_HEAD_PARITY_ERR, 1031 C_PIO_LAST_RETURNED_CNT_PARITY_ERR, 1032 C_PIO_CURRENT_FREE_CNT_PARITY_ERR, 1033 C_PIO_RSVD_31_ERR, 1034 C_PIO_RSVD_30_ERR, 1035 C_PIO_PPMC_SOP_LEN_ERR, 1036 C_PIO_PPMC_BQC_MEM_PARITY_ERR, 1037 C_PIO_VL_FIFO_PARITY_ERR, 1038 C_PIO_VLF_SOP_PARITY_ERR, 1039 C_PIO_VLF_V1_LEN_PARITY_ERR, 1040 C_PIO_BLOCK_QW_COUNT_PARITY_ERR, 1041 C_PIO_WRITE_QW_VALID_PARITY_ERR, 1042 C_PIO_STATE_MACHINE_ERR, 1043 C_PIO_WRITE_DATA_PARITY_ERR, 1044 C_PIO_HOST_ADDR_MEM_COR_ERR, 1045 C_PIO_HOST_ADDR_MEM_UNC_ERR, 1046 C_PIO_PKT_EVICT_SM_OR_ARM_SM_ERR, 1047 C_PIO_INIT_SM_IN_ERR, 1048 C_PIO_PPMC_PBL_FIFO_ERR, 1049 C_PIO_CREDIT_RET_FIFO_PARITY_ERR, 1050 C_PIO_V1_LEN_MEM_BANK1_COR_ERR, 1051 C_PIO_V1_LEN_MEM_BANK0_COR_ERR, 1052 C_PIO_V1_LEN_MEM_BANK1_UNC_ERR, 1053 C_PIO_V1_LEN_MEM_BANK0_UNC_ERR, 1054 C_PIO_SM_PKT_RESET_PARITY_ERR, 1055 C_PIO_PKT_EVICT_FIFO_PARITY_ERR, 1056 C_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR, 1057 C_PIO_SBRDCTL_CRREL_PARITY_ERR, 1058 C_PIO_PEC_FIFO_PARITY_ERR, 1059 C_PIO_PCC_FIFO_PARITY_ERR, 1060 C_PIO_SB_MEM_FIFO1_ERR, 1061 C_PIO_SB_MEM_FIFO0_ERR, 1062 C_PIO_CSR_PARITY_ERR, 1063 C_PIO_WRITE_ADDR_PARITY_ERR, 1064 C_PIO_WRITE_BAD_CTXT_ERR, 1065 /* SendDmaErrStatus */ 1066 C_SDMA_PCIE_REQ_TRACKING_COR_ERR, 1067 C_SDMA_PCIE_REQ_TRACKING_UNC_ERR, 1068 C_SDMA_CSR_PARITY_ERR, 1069 C_SDMA_RPY_TAG_ERR, 1070 /* SendEgressErrStatus */ 1071 C_TX_READ_PIO_MEMORY_CSR_UNC_ERR, 1072 C_TX_READ_SDMA_MEMORY_CSR_UNC_ERR, 1073 C_TX_EGRESS_FIFO_COR_ERR, 1074 C_TX_READ_PIO_MEMORY_COR_ERR, 1075 C_TX_READ_SDMA_MEMORY_COR_ERR, 1076 C_TX_SB_HDR_COR_ERR, 1077 C_TX_CREDIT_OVERRUN_ERR, 1078 C_TX_LAUNCH_FIFO8_COR_ERR, 1079 C_TX_LAUNCH_FIFO7_COR_ERR, 1080 C_TX_LAUNCH_FIFO6_COR_ERR, 1081 C_TX_LAUNCH_FIFO5_COR_ERR, 1082 C_TX_LAUNCH_FIFO4_COR_ERR, 1083 C_TX_LAUNCH_FIFO3_COR_ERR, 1084 C_TX_LAUNCH_FIFO2_COR_ERR, 1085 C_TX_LAUNCH_FIFO1_COR_ERR, 1086 C_TX_LAUNCH_FIFO0_COR_ERR, 1087 C_TX_CREDIT_RETURN_VL_ERR, 1088 C_TX_HCRC_INSERTION_ERR, 1089 C_TX_EGRESS_FIFI_UNC_ERR, 1090 C_TX_READ_PIO_MEMORY_UNC_ERR, 1091 C_TX_READ_SDMA_MEMORY_UNC_ERR, 1092 C_TX_SB_HDR_UNC_ERR, 1093 C_TX_CREDIT_RETURN_PARITY_ERR, 1094 C_TX_LAUNCH_FIFO8_UNC_OR_PARITY_ERR, 1095 C_TX_LAUNCH_FIFO7_UNC_OR_PARITY_ERR, 1096 C_TX_LAUNCH_FIFO6_UNC_OR_PARITY_ERR, 1097 C_TX_LAUNCH_FIFO5_UNC_OR_PARITY_ERR, 1098 C_TX_LAUNCH_FIFO4_UNC_OR_PARITY_ERR, 1099 C_TX_LAUNCH_FIFO3_UNC_OR_PARITY_ERR, 1100 C_TX_LAUNCH_FIFO2_UNC_OR_PARITY_ERR, 1101 C_TX_LAUNCH_FIFO1_UNC_OR_PARITY_ERR, 1102 C_TX_LAUNCH_FIFO0_UNC_OR_PARITY_ERR, 1103 C_TX_SDMA15_DISALLOWED_PACKET_ERR, 1104 C_TX_SDMA14_DISALLOWED_PACKET_ERR, 1105 C_TX_SDMA13_DISALLOWED_PACKET_ERR, 1106 C_TX_SDMA12_DISALLOWED_PACKET_ERR, 1107 C_TX_SDMA11_DISALLOWED_PACKET_ERR, 1108 C_TX_SDMA10_DISALLOWED_PACKET_ERR, 1109 C_TX_SDMA9_DISALLOWED_PACKET_ERR, 1110 C_TX_SDMA8_DISALLOWED_PACKET_ERR, 1111 C_TX_SDMA7_DISALLOWED_PACKET_ERR, 1112 C_TX_SDMA6_DISALLOWED_PACKET_ERR, 1113 C_TX_SDMA5_DISALLOWED_PACKET_ERR, 1114 C_TX_SDMA4_DISALLOWED_PACKET_ERR, 1115 C_TX_SDMA3_DISALLOWED_PACKET_ERR, 1116 C_TX_SDMA2_DISALLOWED_PACKET_ERR, 1117 C_TX_SDMA1_DISALLOWED_PACKET_ERR, 1118 C_TX_SDMA0_DISALLOWED_PACKET_ERR, 1119 C_TX_CONFIG_PARITY_ERR, 1120 C_TX_SBRD_CTL_CSR_PARITY_ERR, 1121 C_TX_LAUNCH_CSR_PARITY_ERR, 1122 C_TX_ILLEGAL_CL_ERR, 1123 C_TX_SBRD_CTL_STATE_MACHINE_PARITY_ERR, 1124 C_TX_RESERVED_10, 1125 C_TX_RESERVED_9, 1126 C_TX_SDMA_LAUNCH_INTF_PARITY_ERR, 1127 C_TX_PIO_LAUNCH_INTF_PARITY_ERR, 1128 C_TX_RESERVED_6, 1129 C_TX_INCORRECT_LINK_STATE_ERR, 1130 C_TX_LINK_DOWN_ERR, 1131 C_TX_EGRESS_FIFO_UNDERRUN_OR_PARITY_ERR, 1132 C_TX_RESERVED_2, 1133 C_TX_PKT_INTEGRITY_MEM_UNC_ERR, 1134 C_TX_PKT_INTEGRITY_MEM_COR_ERR, 1135 /* SendErrStatus */ 1136 C_SEND_CSR_WRITE_BAD_ADDR_ERR, 1137 C_SEND_CSR_READ_BAD_ADD_ERR, 1138 C_SEND_CSR_PARITY_ERR, 1139 /* SendCtxtErrStatus */ 1140 C_PIO_WRITE_OUT_OF_BOUNDS_ERR, 1141 C_PIO_WRITE_OVERFLOW_ERR, 1142 C_PIO_WRITE_CROSSES_BOUNDARY_ERR, 1143 C_PIO_DISALLOWED_PACKET_ERR, 1144 C_PIO_INCONSISTENT_SOP_ERR, 1145 /*SendDmaEngErrStatus */ 1146 C_SDMA_HEADER_REQUEST_FIFO_COR_ERR, 1147 C_SDMA_HEADER_STORAGE_COR_ERR, 1148 C_SDMA_PACKET_TRACKING_COR_ERR, 1149 C_SDMA_ASSEMBLY_COR_ERR, 1150 C_SDMA_DESC_TABLE_COR_ERR, 1151 C_SDMA_HEADER_REQUEST_FIFO_UNC_ERR, 1152 C_SDMA_HEADER_STORAGE_UNC_ERR, 1153 C_SDMA_PACKET_TRACKING_UNC_ERR, 1154 C_SDMA_ASSEMBLY_UNC_ERR, 1155 C_SDMA_DESC_TABLE_UNC_ERR, 1156 C_SDMA_TIMEOUT_ERR, 1157 C_SDMA_HEADER_LENGTH_ERR, 1158 C_SDMA_HEADER_ADDRESS_ERR, 1159 C_SDMA_HEADER_SELECT_ERR, 1160 C_SMDA_RESERVED_9, 1161 C_SDMA_PACKET_DESC_OVERFLOW_ERR, 1162 C_SDMA_LENGTH_MISMATCH_ERR, 1163 C_SDMA_HALT_ERR, 1164 C_SDMA_MEM_READ_ERR, 1165 C_SDMA_FIRST_DESC_ERR, 1166 C_SDMA_TAIL_OUT_OF_BOUNDS_ERR, 1167 C_SDMA_TOO_LONG_ERR, 1168 C_SDMA_GEN_MISMATCH_ERR, 1169 C_SDMA_WRONG_DW_ERR, 1170 DEV_CNTR_LAST /* Must be kept last */ 1171 }; 1172 1173 /* Per port counter indexes */ 1174 enum { 1175 C_TX_UNSUP_VL = 0, 1176 C_TX_INVAL_LEN, 1177 C_TX_MM_LEN_ERR, 1178 C_TX_UNDERRUN, 1179 C_TX_FLOW_STALL, 1180 C_TX_DROPPED, 1181 C_TX_HDR_ERR, 1182 C_TX_PKT, 1183 C_TX_WORDS, 1184 C_TX_WAIT, 1185 C_TX_FLIT_VL, 1186 C_TX_PKT_VL, 1187 C_TX_WAIT_VL, 1188 C_RX_PKT, 1189 C_RX_WORDS, 1190 C_SW_LINK_DOWN, 1191 C_SW_LINK_UP, 1192 C_SW_UNKNOWN_FRAME, 1193 C_SW_XMIT_DSCD, 1194 C_SW_XMIT_DSCD_VL, 1195 C_SW_XMIT_CSTR_ERR, 1196 C_SW_RCV_CSTR_ERR, 1197 C_SW_IBP_LOOP_PKTS, 1198 C_SW_IBP_RC_RESENDS, 1199 C_SW_IBP_RNR_NAKS, 1200 C_SW_IBP_OTHER_NAKS, 1201 C_SW_IBP_RC_TIMEOUTS, 1202 C_SW_IBP_PKT_DROPS, 1203 C_SW_IBP_DMA_WAIT, 1204 C_SW_IBP_RC_SEQNAK, 1205 C_SW_IBP_RC_DUPREQ, 1206 C_SW_IBP_RDMA_SEQ, 1207 C_SW_IBP_UNALIGNED, 1208 C_SW_IBP_SEQ_NAK, 1209 C_SW_IBP_RC_CRWAITS, 1210 C_SW_CPU_RC_ACKS, 1211 C_SW_CPU_RC_QACKS, 1212 C_SW_CPU_RC_DELAYED_COMP, 1213 C_RCV_HDR_OVF_0, 1214 C_RCV_HDR_OVF_1, 1215 C_RCV_HDR_OVF_2, 1216 C_RCV_HDR_OVF_3, 1217 C_RCV_HDR_OVF_4, 1218 C_RCV_HDR_OVF_5, 1219 C_RCV_HDR_OVF_6, 1220 C_RCV_HDR_OVF_7, 1221 C_RCV_HDR_OVF_8, 1222 C_RCV_HDR_OVF_9, 1223 C_RCV_HDR_OVF_10, 1224 C_RCV_HDR_OVF_11, 1225 C_RCV_HDR_OVF_12, 1226 C_RCV_HDR_OVF_13, 1227 C_RCV_HDR_OVF_14, 1228 C_RCV_HDR_OVF_15, 1229 C_RCV_HDR_OVF_16, 1230 C_RCV_HDR_OVF_17, 1231 C_RCV_HDR_OVF_18, 1232 C_RCV_HDR_OVF_19, 1233 C_RCV_HDR_OVF_20, 1234 C_RCV_HDR_OVF_21, 1235 C_RCV_HDR_OVF_22, 1236 C_RCV_HDR_OVF_23, 1237 C_RCV_HDR_OVF_24, 1238 C_RCV_HDR_OVF_25, 1239 C_RCV_HDR_OVF_26, 1240 C_RCV_HDR_OVF_27, 1241 C_RCV_HDR_OVF_28, 1242 C_RCV_HDR_OVF_29, 1243 C_RCV_HDR_OVF_30, 1244 C_RCV_HDR_OVF_31, 1245 C_RCV_HDR_OVF_32, 1246 C_RCV_HDR_OVF_33, 1247 C_RCV_HDR_OVF_34, 1248 C_RCV_HDR_OVF_35, 1249 C_RCV_HDR_OVF_36, 1250 C_RCV_HDR_OVF_37, 1251 C_RCV_HDR_OVF_38, 1252 C_RCV_HDR_OVF_39, 1253 C_RCV_HDR_OVF_40, 1254 C_RCV_HDR_OVF_41, 1255 C_RCV_HDR_OVF_42, 1256 C_RCV_HDR_OVF_43, 1257 C_RCV_HDR_OVF_44, 1258 C_RCV_HDR_OVF_45, 1259 C_RCV_HDR_OVF_46, 1260 C_RCV_HDR_OVF_47, 1261 C_RCV_HDR_OVF_48, 1262 C_RCV_HDR_OVF_49, 1263 C_RCV_HDR_OVF_50, 1264 C_RCV_HDR_OVF_51, 1265 C_RCV_HDR_OVF_52, 1266 C_RCV_HDR_OVF_53, 1267 C_RCV_HDR_OVF_54, 1268 C_RCV_HDR_OVF_55, 1269 C_RCV_HDR_OVF_56, 1270 C_RCV_HDR_OVF_57, 1271 C_RCV_HDR_OVF_58, 1272 C_RCV_HDR_OVF_59, 1273 C_RCV_HDR_OVF_60, 1274 C_RCV_HDR_OVF_61, 1275 C_RCV_HDR_OVF_62, 1276 C_RCV_HDR_OVF_63, 1277 C_RCV_HDR_OVF_64, 1278 C_RCV_HDR_OVF_65, 1279 C_RCV_HDR_OVF_66, 1280 C_RCV_HDR_OVF_67, 1281 C_RCV_HDR_OVF_68, 1282 C_RCV_HDR_OVF_69, 1283 C_RCV_HDR_OVF_70, 1284 C_RCV_HDR_OVF_71, 1285 C_RCV_HDR_OVF_72, 1286 C_RCV_HDR_OVF_73, 1287 C_RCV_HDR_OVF_74, 1288 C_RCV_HDR_OVF_75, 1289 C_RCV_HDR_OVF_76, 1290 C_RCV_HDR_OVF_77, 1291 C_RCV_HDR_OVF_78, 1292 C_RCV_HDR_OVF_79, 1293 C_RCV_HDR_OVF_80, 1294 C_RCV_HDR_OVF_81, 1295 C_RCV_HDR_OVF_82, 1296 C_RCV_HDR_OVF_83, 1297 C_RCV_HDR_OVF_84, 1298 C_RCV_HDR_OVF_85, 1299 C_RCV_HDR_OVF_86, 1300 C_RCV_HDR_OVF_87, 1301 C_RCV_HDR_OVF_88, 1302 C_RCV_HDR_OVF_89, 1303 C_RCV_HDR_OVF_90, 1304 C_RCV_HDR_OVF_91, 1305 C_RCV_HDR_OVF_92, 1306 C_RCV_HDR_OVF_93, 1307 C_RCV_HDR_OVF_94, 1308 C_RCV_HDR_OVF_95, 1309 C_RCV_HDR_OVF_96, 1310 C_RCV_HDR_OVF_97, 1311 C_RCV_HDR_OVF_98, 1312 C_RCV_HDR_OVF_99, 1313 C_RCV_HDR_OVF_100, 1314 C_RCV_HDR_OVF_101, 1315 C_RCV_HDR_OVF_102, 1316 C_RCV_HDR_OVF_103, 1317 C_RCV_HDR_OVF_104, 1318 C_RCV_HDR_OVF_105, 1319 C_RCV_HDR_OVF_106, 1320 C_RCV_HDR_OVF_107, 1321 C_RCV_HDR_OVF_108, 1322 C_RCV_HDR_OVF_109, 1323 C_RCV_HDR_OVF_110, 1324 C_RCV_HDR_OVF_111, 1325 C_RCV_HDR_OVF_112, 1326 C_RCV_HDR_OVF_113, 1327 C_RCV_HDR_OVF_114, 1328 C_RCV_HDR_OVF_115, 1329 C_RCV_HDR_OVF_116, 1330 C_RCV_HDR_OVF_117, 1331 C_RCV_HDR_OVF_118, 1332 C_RCV_HDR_OVF_119, 1333 C_RCV_HDR_OVF_120, 1334 C_RCV_HDR_OVF_121, 1335 C_RCV_HDR_OVF_122, 1336 C_RCV_HDR_OVF_123, 1337 C_RCV_HDR_OVF_124, 1338 C_RCV_HDR_OVF_125, 1339 C_RCV_HDR_OVF_126, 1340 C_RCV_HDR_OVF_127, 1341 C_RCV_HDR_OVF_128, 1342 C_RCV_HDR_OVF_129, 1343 C_RCV_HDR_OVF_130, 1344 C_RCV_HDR_OVF_131, 1345 C_RCV_HDR_OVF_132, 1346 C_RCV_HDR_OVF_133, 1347 C_RCV_HDR_OVF_134, 1348 C_RCV_HDR_OVF_135, 1349 C_RCV_HDR_OVF_136, 1350 C_RCV_HDR_OVF_137, 1351 C_RCV_HDR_OVF_138, 1352 C_RCV_HDR_OVF_139, 1353 C_RCV_HDR_OVF_140, 1354 C_RCV_HDR_OVF_141, 1355 C_RCV_HDR_OVF_142, 1356 C_RCV_HDR_OVF_143, 1357 C_RCV_HDR_OVF_144, 1358 C_RCV_HDR_OVF_145, 1359 C_RCV_HDR_OVF_146, 1360 C_RCV_HDR_OVF_147, 1361 C_RCV_HDR_OVF_148, 1362 C_RCV_HDR_OVF_149, 1363 C_RCV_HDR_OVF_150, 1364 C_RCV_HDR_OVF_151, 1365 C_RCV_HDR_OVF_152, 1366 C_RCV_HDR_OVF_153, 1367 C_RCV_HDR_OVF_154, 1368 C_RCV_HDR_OVF_155, 1369 C_RCV_HDR_OVF_156, 1370 C_RCV_HDR_OVF_157, 1371 C_RCV_HDR_OVF_158, 1372 C_RCV_HDR_OVF_159, 1373 PORT_CNTR_LAST /* Must be kept last */ 1374 }; 1375 1376 u64 get_all_cpu_total(u64 __percpu *cntr); 1377 void hfi1_start_cleanup(struct hfi1_devdata *dd); 1378 void hfi1_clear_tids(struct hfi1_ctxtdata *rcd); 1379 void hfi1_init_ctxt(struct send_context *sc); 1380 void hfi1_put_tid(struct hfi1_devdata *dd, u32 index, 1381 u32 type, unsigned long pa, u16 order); 1382 void hfi1_quiet_serdes(struct hfi1_pportdata *ppd); 1383 void hfi1_rcvctrl(struct hfi1_devdata *dd, unsigned int op, 1384 struct hfi1_ctxtdata *rcd); 1385 u32 hfi1_read_cntrs(struct hfi1_devdata *dd, char **namep, u64 **cntrp); 1386 u32 hfi1_read_portcntrs(struct hfi1_pportdata *ppd, char **namep, u64 **cntrp); 1387 int hfi1_get_ib_cfg(struct hfi1_pportdata *ppd, int which); 1388 int hfi1_set_ib_cfg(struct hfi1_pportdata *ppd, int which, u32 val); 1389 int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd, 1390 u16 jkey); 1391 int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt); 1392 int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt, 1393 u16 pkey); 1394 int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt); 1395 void hfi1_read_link_quality(struct hfi1_devdata *dd, u8 *link_quality); 1396 void hfi1_init_vnic_rsm(struct hfi1_devdata *dd); 1397 void hfi1_deinit_vnic_rsm(struct hfi1_devdata *dd); 1398 1399 irqreturn_t general_interrupt(int irq, void *data); 1400 irqreturn_t sdma_interrupt(int irq, void *data); 1401 irqreturn_t receive_context_interrupt(int irq, void *data); 1402 irqreturn_t receive_context_thread(int irq, void *data); 1403 irqreturn_t receive_context_interrupt_napi(int irq, void *data); 1404 1405 int set_intr_bits(struct hfi1_devdata *dd, u16 first, u16 last, bool set); 1406 void init_qsfp_int(struct hfi1_devdata *dd); 1407 void clear_all_interrupts(struct hfi1_devdata *dd); 1408 void remap_intr(struct hfi1_devdata *dd, int isrc, int msix_intr); 1409 void remap_sdma_interrupts(struct hfi1_devdata *dd, int engine, int msix_intr); 1410 void reset_interrupts(struct hfi1_devdata *dd); 1411 u8 hfi1_get_qp_map(struct hfi1_devdata *dd, u8 idx); 1412 void hfi1_init_aip_rsm(struct hfi1_devdata *dd); 1413 void hfi1_deinit_aip_rsm(struct hfi1_devdata *dd); 1414 1415 /* 1416 * Interrupt source table. 1417 * 1418 * Each entry is an interrupt source "type". It is ordered by increasing 1419 * number. 1420 */ 1421 struct is_table { 1422 int start; /* interrupt source type start */ 1423 int end; /* interrupt source type end */ 1424 /* routine that returns the name of the interrupt source */ 1425 char *(*is_name)(char *name, size_t size, unsigned int source); 1426 /* routine to call when receiving an interrupt */ 1427 void (*is_int)(struct hfi1_devdata *dd, unsigned int source); 1428 }; 1429 1430 #endif /* _CHIP_H */ 1431