Home
last modified time | relevance | path

Searched refs:CVMX_PESCX_CTL_STATUS2 (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/arch/mips/pci/
H A Dpcie-octeon.c836 pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port)); in __cvmx_pcie_rc_initialize_gen1()
838 cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port), pescx_ctl_status2.u64); in __cvmx_pcie_rc_initialize_gen1()
842 if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port), in __cvmx_pcie_rc_initialize_gen1()
854 pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port)); in __cvmx_pcie_rc_initialize_gen1()
/openbmc/linux/arch/mips/include/asm/octeon/
H A Dcvmx-pescx-defs.h37 #define CVMX_PESCX_CTL_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1)… macro