Searched refs:CTL0 (Results 1 – 5 of 5) sorted by relevance
| /openbmc/linux/drivers/dma/ |
| H A D | pch_dma.c | 210 val = dma_readl(pd, CTL0); in pdc_set_dir()
225 dma_writel(pd, CTL0, val); in pdc_set_dir()
261 val = dma_readl(pd, CTL0); in pdc_set_mode()
265 dma_writel(pd, CTL0, val); in pdc_set_mode()
744 pd->regs.dma_ctl0 = dma_readl(pd, CTL0); in pch_dma_save_regs()
767 dma_writel(pd, CTL0, pd->regs.dma_ctl0); in pch_dma_restore_regs()
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| /openbmc/u-boot/board/freescale/mx51evk/ |
| H A D | imximage.cfg | 100 /* Write to CTL0 */
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| /openbmc/linux/Documentation/devicetree/bindings/display/ |
| H A D | lvds.yaml | 77 CTL0: HSync
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| /openbmc/qemu/include/hw/misc/ |
| H A D | xlnx-versal-cframe-reg.h | 74 REG32(CTL0, 0x80)
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| /openbmc/linux/drivers/soc/mediatek/ |
| H A D | mtk-svs.c | 235 CTL0, enumerator
293 [CTL0] = 0xc88,
1129 svs_writel_relaxed(svsp, svsb->ctl0, CTL0); in svs_set_bank_phase()
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