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Searched refs:CSR_VSTIMECMPH (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/arch/riscv/kvm/
H A Dvcpu_timer.c76 csr_write(CSR_VSTIMECMPH, ncycles >> 32); in kvm_riscv_vcpu_update_vstimecmp()
310 csr_write(CSR_VSTIMECMPH, (u32)(t->next_cycles >> 32)); in kvm_riscv_vcpu_timer_restore()
331 t->next_cycles |= (u64)csr_read(CSR_VSTIMECMPH) << 32; in kvm_riscv_vcpu_timer_sync()
/openbmc/linux/arch/riscv/include/asm/
H A Dcsr.h310 #define CSR_VSTIMECMPH 0x25D macro
/openbmc/qemu/target/riscv/
H A Dcpu_bits.h276 #define CSR_VSTIMECMPH 0x25D macro
H A Dcsr.c465 if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) { in sstc()
5179 [CSR_VSTIMECMPH] = { "vstimecmph", sstc_32, read_vstimecmph,