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Searched refs:CSR_STVEC (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/riscv/include/asm/
H A Dencoding.h179 #define CSR_STVEC 0x105 macro
/openbmc/qemu/target/riscv/
H A Dcpu_bits.h201 #define CSR_STVEC 0x105 macro
H A Dcpu.c551 CSR_STVEC, in riscv_cpu_dump_state()
H A Dcsr.c4119 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); in write_stvec()
6013 [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec },