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Searched refs:CSR_SSTATEEN0 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h201 #define CSR_SSTATEEN0 0x10C macro
H A Dcsr.c432 int index = csrno - CSR_SSTATEEN0; in sstateen()
2710 int index = csrno - CSR_SSTATEEN0; in read_sstateen()
2724 int index = csrno - CSR_SSTATEEN0; in write_sstateen()
5150 [CSR_SSTATEEN0] = { "sstateen0", sstateen, read_sstateen, write_sstateen0,