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Searched refs:CSR_SPMBASE (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h522 #define CSR_SPMBASE 0x1c2 macro
H A Dcpu.c799 CSR_SPMBASE, in riscv_cpu_dump_state()
H A Dcsr.c5335 [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase,