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Searched refs:CSR_SEPC (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/riscv/include/asm/
H A Dencoding.h182 #define CSR_SEPC 0x141 macro
/openbmc/qemu/target/riscv/
H A Dcpu_bits.h218 #define CSR_SEPC 0x141 macro
H A Dcpu.c554 CSR_SEPC, in riscv_cpu_dump_state()
H A Dcsr.c6023 [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc },