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Searched refs:CSR_PMPCFG0 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/riscv/include/asm/
H A Dencoding.h229 #define CSR_PMPCFG0 0x3a0 macro
/openbmc/qemu/target/riscv/
H A Dcpu_bits.h371 #define CSR_PMPCFG0 0x3a0 macro
H A Dcsr.c749 uint32_t reg_index = csrno - CSR_PMPCFG0; in pmp()
5302 uint32_t reg_index = csrno - CSR_PMPCFG0; in read_pmpcfg()
5311 uint32_t reg_index = csrno - CSR_PMPCFG0; in write_pmpcfg()
6169 [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },