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Searched refs:CSR_MSTATEEN1 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h308 #define CSR_MSTATEEN1 0x30D macro
H A Dcsr.c5020 [CSR_MSTATEEN1] = { "mstateen1", mstateen, read_mstateen,