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Searched refs:CSR_MSTATEEN0H (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h307 #define CSR_MSTATEEN0H 0x31C macro
H A Dcsr.c2518 *val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32; in read_mstateenh()
2528 reg = &env->mstateen[csrno - CSR_MSTATEEN0H]; in write_mstateenh()
5017 [CSR_MSTATEEN0H] = { "mstateen0h", mstateen, read_mstateenh,