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Searched refs:CSR_MIP (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/riscv/include/asm/
H A Dencoding.h228 #define CSR_MIP 0x344 macro
/openbmc/qemu/target/riscv/
H A Dcpu_bits.h170 #define CSR_MIP 0x344 macro
H A Dcpu.c544 CSR_MIP, in riscv_cpu_dump_state()
H A Dcsr.c3841 ret = rmw_mip(env, CSR_MIP, &ret_mip, new_val, wr_mask_mip); in rmw_mvip64()
5888 [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip },