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Searched refs:CSR_MIDELEGH (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/arch/riscv/include/asm/
H A Dcsr.h384 #define CSR_MIDELEGH 0x313 macro
/openbmc/qemu/target/riscv/
H A Dcpu_bits.h182 #define CSR_MIDELEGH 0x313 macro
H A Dcsr.c4996 [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },