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Searched refs:CSR_MIDELEG (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/arch/riscv/include/asm/
H A Dencoding.h191 #define CSR_MIDELEG 0x303 macro
/openbmc/linux/arch/riscv/include/asm/
H A Dcsr.h355 #define CSR_MIDELEG 0x303 macro
/openbmc/qemu/target/riscv/
H A Dcpu_bits.h155 #define CSR_MIDELEG 0x303 macro
H A Dcpu.c776 CSR_MIDELEG, in riscv_cpu_dump_state()
H A Dcsr.c5050 [CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg },